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Design >> RF Design >> RF Amplifier output buffer
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Message started by aaron_do on Jun 29^th, 2006, 12:38am

Title: RF Amplifier output buffer
Post by aaron_do on Jun 29^th, 2006, 12:38am

Hi All,

I'm designing an amplifier to work at 2.4 GHz using CMOS, and the main performance i wish to measure are gain and noise figure. However, my Amp has no output matching. I had a little trouble designing a good output buffer, so i got some advice that i could use a simple resistive divider. My Amp uses a resistive load of 1 kohm and this was split into a 975 ohm and 50 ohm. Since the output port is 50 ohm, the overall load is still 1kohm and I get good matching. To find the gain i simply multiply by 40 ((975 + 50//50)/(50//50)). The noise figure will be more difficult to calculate but i believe it is possible given the NF and loss of the attenuator. Here is a pic of what the amp basically looks like.

^VDD
l
l
<
<50 ohm
< 50 ohm port
l-----vvvv----gnd
<
<975 ohm
<
l
l I= gm*Vin
l
location X

So my question is does anybody know any reason why I should avoid this method? In simulation, the overall NF raised from around 5 dB at location X to around 15 dB at the output port. Also does anyone have any tips on de-embedding the noise?

thanks,
Aaron

Title: Re: RF Amplifier output buffer
Post by cybq on Jun 29^th, 2006, 5:54pm

yeah, you are difficult to design a matching net to match 1K to 50ohm, which otherwise is a net 15nH parallel adding 0.3pF series. I think design a buffer is a good choice, with a more power comsumption
expence.

Title: Re: RF Amplifier output buffer
Post by loose-electron on Aug 3^rd, 2006, 4:39pm

Time to start including your capacitive parasitic loads. For everything, resistors, output loads, metals, etc.

At 2-3GHz I really doubt that a load resistance in 1k going to fly. Besides, you are tossing all your gain away in the resistor divider. Also, when you start doing noise analysis that 1K resistance is going to be very noisy.

Consider dropping your load resistance down to a 200-500 (or lower!) ohm region and come out directly without a buffer. More current in one stage, but no buffer, and less noise.

Besides, CMOS Source folowers really don't work that well at RF.

Jerry

Title: Re: RF Amplifier output buffer
Post by simon2 on Aug 4^th, 2006, 3:02am

Aaron,
I would avoid the resistive attenuator on the output
- use either a pi matching network centred at 2.5GHz with a
loaded Q around 5 and accept the loss of power at 2 and
3 GHz:

50R o---o-----15nH----o----o 1K
| |
0p7 0p33
| |
----- -----
//// ////

or a "T" network if a DC block is required:

50R o----0p3-----o-----0p12----o 1K
|
15nH
|
-----
////

which may become a bit difficult to implement once you accomodate
the MOS parasitic elements. It would be preferable to use a 5:1
transformer (an interesting challenge on chip; but "do-able" and
with an insertion loss of about 1.5dB) which can be implemented off
chip using pcb transmission lines.

You will get a noise figue of about 5-6dB (not 15) and a gain
of about 15dB (not 25.5*) for such a common source amplifier
with a "standard" 0.18um CMOS process.

* I have assumed that your voltage gain is 40x, making the
overall power gain, given a good 50R input match:

20.log((40) - 10.log((1000/50)^0.5)

Actually you should be calculating the MAG (maximum available
gain, or transducer gain Gum) which includes a knowledge of both
the input and output impedances and the matching to them.

Take a look at:

http://www.silicondevices.com/Resources/AppsNotes/SparametersInWinSpice.html

if you would like to get an idea of how this may be done in simulation.

Cheers,
SimonH.

Title: Re: RF Amplifier output buffer
Post by simon2 on Aug 4^th, 2006, 3:21am

Sorry, that gain calculation was incorrect, it should have been:

20.log((40) - 20.log((1000/50)^0.5) = 6dB

although in reality you are not likely to get a voltage gain of 40
from your CMOS device, a power gain of 40 would be more
believable giving:

10.log((40) - 10.log(1000/50) = 3dB

Cheers,
SimonH.

Title: Re: RF Amplifier output buffer
Post by aaron_do on Aug 4^th, 2006, 6:52am

Hi all,

thanks for the replies. I don't think i was very clear in my question. The amplifier will not actually be driving a 50 ohm load. It is driving a capacitive load. My current consumption has been kept very low (~500 uA) which allows me to use a resistive load at the output without severly limiting the voltage headroom. Thus the output looks like a single pole low-pass filter.

However, for on-wafer testing it is convenient to use S-parameters. Therefore i need to match to 50 ohm. I need to avoid using a LC matching network because i am trying to cut down on chip area, and also I want to preserve the actual output characteristics of the amp. As pointed out by "loose-electron", source followers don't work well at RF and i wouldn't be able to accurately tell what kind of loss is being introduced by it...therefore i chose the resistive divider. Because of its simplicity i can easily de-embed the divider.

Thanks for all the replies...i've actually already sent the circuit for tapeout so...

Aaron