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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> slew rate simulation question https://designers-guide.org/forum/YaBB.pl?num=1151668781 Message started by chungmnig on Jun 30th, 2006, 4:59am |
Title: slew rate simulation question Post by chungmnig on Jun 30th, 2006, 4:59am Hi~~ i have a question about how to simulate slew rate in fully differential switched cap CMFB OPA? like attached file Why using 1M Ohm? is more larger more better? and why using 6.8pF cap as unit gain , why don't use other number? thanks~~!! |
Title: Re: slew rate simulation question Post by sheldon on Jun 30th, 2006, 6:11pm Chungming, 1) Using a 1M resistor allows the OTA to setup to the correct input dc common level without requiring the switching. In general, a larger value would be better since it effects the circuit less. 2) The value of the capacitor is not related to the gain. The ratio of the input capacitor and feedback capacitor sets the gain, -Cin/Cf. Having said that, there are some other things you might want to consider when creating testbenches: 1) My philosophy would be that the testbench should not effect the measurement. So I would use an analysis dependent switch VCM (vcm 0) vsource dc=common_mode_level SCN ( vcm inp) switch position=1 ac_position=0 SCI ( vcm inn) switch position=1 ac_position=0 Now for the dc operating point calculation, the dc level is the forced to the common-mode level, however, for ac analysis the nodes float. 2) As mentioned, the ratio of the input and feedback capacitor ratio determine the gain, not the absolute value of the capacitor. However, slew rate is determined by the maximum value of the output current and the total capacitance at the output node. slew rate = dV/dT = Iout, max/ Ctotal = Iout, total / ( Cfeedback + Cload) or slew rate = Iout, max / ( 6.8pF + 15pF). So slew rate is proportional to the value of the feedback capacitor. Additional discussion: If you have access to Ken's book "The Designer's Guide to SPICE and Spectre", you might want to review pages 67 to 106. He discusses various methods for measuring the stability of feedback amplifiers. He also illustrates some "best practices for testbench development". Sorry my version is a little repititive for emphasis. a) If possible, make the measurement in-situ, that is, as the circuit is intended to be used. The results for the testbenches with the LC network to "open" the loop are not the same as the measurements with the loop closed. b) Observing the phenomena should not alter the phenomena, that is, making a measurement should not change the result. For example, using the VCVS eliminates the effect of the feedback netwotk loading the circuit and changes the results. c) Measure the parameter of interest, that is, if you want to understand stability measure the loop gain not the open loop gain of the amplifier. The two port measurement allows the designer to separately measure the forward and reverse characteristics. Using this information, it is easy to see why using the amplifier open loop gain is not appropriate for analyzing loop gain(for the example circuit). At high frequency, the effect of loading on feedback network can not be ignored when calculating the loop characterisitcs. Best Regards, Sheldon |
Title: Re: slew rate simulation question Post by chungmnig on Jul 1st, 2006, 8:55pm Hi~~~sheldon thanks for your detail reply ~~~ :) and if choose Cload=3p F, feedback & input capccitor = 1pF the attached file is the simulation result slew rate = Iout,max / (Cload+Cfeedbacd) = 33.64u/4p = 8.41 V/us , is it right ? and left diagram of attached file is the Voutp-Voutn result (step =0.4V) , i directly use calculator to calculate slew rate only = 1V/us .......why? ? is using calculator to calculate slew rate not correct? And if i use larger feedback & input capacitor the slew rate will degrade. (Cfeedback & Ci = 5p ,slew rate = 6.9 V/us ) Why not the saame as Cfeedback=1p , slew rate will dependent on not only the ratio of feedback and input but also the value of feedback & input capacitor......??? thanks~~~!!! |
Title: Re: slew rate simulation question Post by sheldon on Jul 3rd, 2006, 3:57am Chungming, First, is the current you show the current in the output transistor or the current in the tail source? There is an assumption when you calculate the slew rate that the circuit's performance is slew rate limited. In your case, it appears that the circuit is bandwidth limited. That is, the pulse response is determined by time constant of the circuit, tau = gm/C. If you look at the current plot, the circuit's response is hardly disturbed from steady-state. In slew rate limiting, the current should go from full off, 0uA, to mid-range, ~30uA[settled], to full on, 60uA, to mid-range, 30uA[settled] and then repeat. There is a dependence on the capacitor ratio because the circuit bandwidth limited. That is, for gain of -3[3pF/1pF] the bandwidth is less than the when the gain is -1[5pF/5pF]. When the gain is -1, the bandwidth is 3x wider and the circuit starts to slew rate limit. Could you try again, with a gain of -1 and Ci=1pF and Cf=1pF? This should eliminate bandwidth as a constraint and the circuit should be slew rate limited. Also, could you describe how you setup the slew rate measurement? Best Regards, Sheldon |
Title: Re: slew rate simulation question Post by sheldon on Jul 3rd, 2006, 4:40pm Chungming, Some additional comments: 1) The difference in bandwidth is 2x not 3x. 2) One other effect maybe contributing the results you see. Slew rate limiting occurs because the input level is outside the "linear range" of the input stage's transconductance, gm. For large differential input voltages, the output current saturates and this saturation causes slew rate limiting. --> To force the amplifier to saturate, increase the input step size. Best Regards, Sheldon |
Title: Re: slew rate simulation question Post by chungmnig on Jul 3rd, 2006, 5:23pm Hi~~~~sheldon~~~~ :) The current is output stage 's current , not tail current. The attached file is my simulation result Right is fully differential OTA with 3pF capacitor load, differential input voltage = 1V . Left above is Ci=Cf=1pF , i think it is not slew rate limit. Left below is Ci=Cf=20pF , the current reach almost zero current , Is it means slew rate limit occurs? Is slew rate = Iout,max/(Cload+Cf) = 302.2u /(3p+20p) = 13.14 V/us ? And why i use the same ratio Ci / Cf =1 , but the behavior of circuit is not the same ? thanks~~~!!!!!! |
Title: Re: slew rate simulation question Post by sheldon on Jul 3rd, 2006, 7:11pm Chungming, It is a little hard to tell how the circuit is working from the schematic, assuming that sources of the n-channels are grounded. Then the output stage of your design has adaptive biasing so the heavier the load the higher the drive current. My previous comments are not applicable when the amplifier has adaptive biasing. Basically, for light loading, 1pF, you see the circuits intrinsic behavior and for heavy loading you see the effect of the adaptive biasing, 20pF. So the difference in the results occurs because the slew rate is boosted for heavier loads. Best Regards, |
Title: Re: slew rate simulation question Post by chungmnig on Jul 3rd, 2006, 8:14pm sheldon~~ :-/ Now i confused.......... This OTA named as "Two-stage Class A/AB" finding in a book "The design of low voltage low power sigma delta modulators" , it is also a JSSC paper. In that book , he say "The two stage class A/AB amplifier combines a simple differential-pair as the first stage with a class A/B second stage wherein push-pull operation is implemented through the use of current mirrors. Slew limiting only occurs in the first stage" Is that means as you said ? And what is adaptive biasing? The attached file is another OTA , Is it has slew rate limiting? the nmos reach zero current, or the current behavior must full off, 0uA, to mid-range, ~30uA "[settled]" like you said? (Cin = Cfeedback =1pF , Cload = 0.4pF) The most important how simulate the slew rate? ...... only simulate first stage? thanks a lot~~!!! |
Title: Re: slew rate simulation question Post by sheldon on Jul 8th, 2006, 2:57am Chungming, From the simulation testbench, it looks like you are simulating slew rate correctly. However, this circuit may not have a simple, single-valued, linear slew rate. The circuit is an two-stage OTA that includes local feedback in the first stage and a push-pull drive in the second stage to boost the slew rate. These enhancements significantly improve dynamic performance of the amplifier. However, they also introduce some non-linearity to the stage, that is, the slew rate is not constant. For larger overdrive the amplifier slews faster. Since it is difficult to measure "slew rate", probably the most important thing to do it to use the actual circuit and input conditions to measure the slew rate. In the end what is important is how the OTA works in your application. Best Regards, Sheldon |
Title: Re: slew rate simulation question Post by chungmnig on Jul 8th, 2006, 9:06pm sheldon~~~~~ I really very appreciate your suggestion~~!!!! :D :D :D |
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