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Simulators >> Circuit Simulators >> Monte carlo simulation for cells
https://designers-guide.org/forum/YaBB.pl?num=1152185107

Message started by hamed on Jul 6^th, 2006, 4:25am

Title: Monte carlo simulation for cells
Post by hamed on Jul 6^th, 2006, 4:25am

Hi all,
I have a designed 4-bit flash ADC, The Monte carlo simulation gives a dc offset "sigma=x" for the unit comparator. I would like to test 16 compartors as a whole ADC for possible dc offset mismatch among them. How I can do it, given that the dc offset of unit compartor is already estimated?
I know that putting a dc source in the input of each comparator and setting different varible names for each one can help, but how about linking these variables distribution to sigma=x which has already been estimated?

Hamed

Title: Re: Monte carlo simulation for cells
Post by achim.graupner on Jul 6^th, 2006, 10:30pm

Hi hamed,
I suppose the simplest solution would be to design a VerilogA-voltage source whose value is random. This can be achieved like

analog begin
@ (initial_step) begin
rrandnum = $rdist_uniform(seed, start_range, end_range);
end
V(pinout) <+ rrandnum ;
end

use the seed value as parameter and assign a different value to each instance of this random voltage source.

An other possibility could be to define new variables in your mcparams-file. But I do not know whether those variables can solely used within model cards or whether there is a link to design variables. Maybe someone else knows.

Regards, achim

Title: Re: Monte carlo simulation for cells
Post by hamed on Jul 11^th, 2006, 2:58am

Hi Achim,
Actually I preferred to try again your second comment, meaning that I made a new library file having a mismatch variable of "voffset" with gaussian distribution and pre-estimated Sigma for each comparator. This "voffset" is a common variable for all voltage sources put at input of each comparator representing the offset; and this way Monte carlo works fine, i.e. automatically varying each voltage source with the proper distrubution independently.
It is instructive to share the cause of the problem I had: in fact I had done the same as above except puting different voltage sources (15 variables) outside of comparators, i.e. voffset1, voffset2, ....,voffset15. Actually the mismatch in statistic part of library file works fine if the variable is in subcircuit, so to be able to ueilize mismatch capabilities of Monte carlo, one has to be careful in using variables in right hirarchy. Note that despite the fact that all comparators share the same subckt, and so the same voltage source with the same name "voffset", the Monte carlo can manage to put different values in the input of the comparators in each run and change them properly in consequent runs.

Hamed