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Design >> RF Design >> PLL stabilitiy
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Message started by mkaragou on Jul 11^th, 2006, 5:35am

Title: PLL stabilitiy
Post by mkaragou on Jul 11^th, 2006, 5:35am

What is the best way to prove the stability of a phase-locked loop by simulation when Spectre is used?

Title: Re: PLL stabilitiy
Post by Eugene on Jul 11^th, 2006, 11:25am

Personally, I don't think any one way is better than another. It comes down to modeling. Do you want to wait for a device level simulation or invest in a faster behavioral model. I have never gotten any meaningful results from just one simulation; I always have to run it several times to get all the parameters and options correct. Device level models run very slow. In a tight schedule, they can limit verification coverage. Furthermore, for PLLs, it is hard to quantify conventional design margins, like phase margin. Behavioral models run fast but you risk missing a critical impairment or making a modeling error. I believe the most rigorous way to assess PLL stability within Spectre is to use both methods and to make sure theyare consistent with each other. On the behavioral side, I would definitely construct a phase domain model, which is inherently behavioral. If I did not have time for a full device level simulation, I might check the phase domain model with a voltage domain behavioral model.

Title: Re: PLL stabilitiy
Post by mkaragou on Jul 12^th, 2006, 4:02am

Ok, lets say I would like to perform a full blown transistor level simulation only, because I am to lazy to create a behavioral model.
And now I want to optimize the the loop filter paramaters to achieve fast phase lock and to ensure stability.

What is the optimum simulation strategy?

Title: Re: PLL stabilitiy
Post by smlogan on Jul 12^th, 2006, 8:28am

mkaragou wrote on Jul 12^th, 2006, 4:02am:

If you have some reasonable gauge of its stability, perhaps a transient simulation to obtain its phase step response might be a means of assessing its stability. Specifically, if you apply an input frequency with a phase step at some time and examine the resulting output phase (by post processing the output freqeuncy response), you can determine how closely ots response is to your expectation. Excessive output phase ringing or overshoot are certainly signs of less phase margin while an excessively slow damped response may indicate excessive damping.

I suppose an advantage of this method is that you are not relying on a behavioral model and any "hidden" subtleties in the specific implementation not captured in the behavioral model. I would also recommend using various phase step sizes as the phase step response may be a string function of the input phase step amplitude. If, for example, your loop has a frequency acquisition aid, its response will differ significantly if the frequency acquisiton aid is invoked.

Just a few thoughts anyway...

Title: Re: PLL stabilitiy
Post by boa on Jul 12^th, 2006, 10:32pm

mkaragou wrote on Jul 12^th, 2006, 4:02am:

Make a behavioral model :) Frequency domain for phase noise, time domain for lock time and transient stability. It will take you 10 times less time to make a behavioral time-domain model then to run transitor-level transient simulation. ;)

Title: Re: PLL stabilitiy
Post by loose-electron on Aug 1^st, 2006, 7:09pm

If both fast lock and good phase noise are a key issue, then you may also want to consider changing the loop gain (and resulting bandwidth) as a function of the lock cycle.

That is a common trick pulled in timing aquisition systems. The analogy I use is "shifting gears" while coming up to speed. Simplest method to implement is changing the current in the charge pump.

When you drop to lower loop gain/BW the phase noise is better. If it is an LO for a mixer, you need to the usual precautions with respect to phase noise and spectral spreading of course.

Jerry