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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> Clock Duty Cycle Correction Circuit https://designers-guide.org/forum/YaBB.pl?num=1153441202 Message started by sachinagg on Jul 20th, 2006, 5:20pm |
Title: Clock Duty Cycle Correction Circuit Post by sachinagg on Jul 20th, 2006, 5:20pm I intend to design a "Clock Duty Cycle Correction Circuit" that can handle input clocks with duty cycle ranging from 20% to 80% and output a clock with 50% duty cycle [with a tolerance of 1%]. Another important requirement for the circuit is LOW JITTER performance as this circuit is meant for providing clock to high performance ADC. I would be grateful if anyone could inform me about some relevenat reference to start the design. Thank You Sachin |
Title: Re: Clock Duty Cycle Correction Circuit Post by huber on Jul 22nd, 2006, 1:23pm Hi Sachin, I've never designed one of these, never even heard of one, but I think something like this should work: If you're clocking an ADC with the output of your circuit, then you probablly only care about jitter on one edge (rising or falling). In this circuit, that edge would be generated by the lower path. There are no delay elements in this path, so jitter will be low. -Dan |
Title: Re: Clock Duty Cycle Correction Circuit Post by huber on Jul 22nd, 2006, 1:28pm One more thing: you would have to initialize the two flip flops to the same value to ensure the correct edge has low jitter. -Dan |
Title: Re: Clock Duty Cycle Correction Circuit Post by huber on Jul 22nd, 2006, 1:39pm Hmm... not qite sure why I put two FFs in there. This is better: -Dan |
Title: Re: Clock Duty Cycle Correction Circuit Post by huber on Jul 22nd, 2006, 1:57pm Whoops, this doesn't work. Output clock is half rate of input. If the input duty cycle range was 25-75% then you could eliminate the flip flop and use an OR gate at the ouput. Maybe. -Dan |
Title: Re: Clock Duty Cycle Correction Circuit Post by smlogan on Jul 23rd, 2006, 8:23pm Hi Sachin, I just designed a duty cycle correction circuit after studying a previous version that was not adequate. A couple of items come to mind... 1. The range of duty cycle correction you must consider and a low jitter solution require a compromise. The larger duty cycle range that you must cover suggest a higher sensitivity to jitter. I'm not sure of the A/D topologyyou are considering. However, the fact that it requires a 50+/- 1% duty cycle suggests that jitter on both edges of the clock is important. The solution I adopted, over silicon process and environmental effects was able to correct between 30% and 70% duty cycles to within 1%. 2. If at all possible, I would suggest examining the impact of distributing a clock to the A/D at twice its current frequency. By dividing the clock locally, if a duty cycle correction circuit is still necessay, you might only have to correct for a 1 or 2% duty cycle error. This will allow a much less jitter sensitive solution. Of course, if the flip flop propagation delay is low enough relative to the clock frequency, a duty cycle correction circuit may not be necessary. Let me know if you have any idea as to the magnitude of phase jitter requirement on the A/D clock. Shawn |
Title: Re: Clock Duty Cycle Correction Circuit Post by ywguo on Aug 4th, 2006, 4:17am Hi, guys, How about a DLL? Select two outputs with 180o phase shift. Then make a clock with 50% duty cycle using those two outputs. But the above method is still complex. A simpler method will make me happy. BG Yawei |
Title: Re: Clock Duty Cycle Correction Circuit Post by loose-electron on Aug 4th, 2006, 8:42am The most efficient way of getting this done sort of ducks the question. Distribute a 2F clock, and locally divide it down by 2. In RF mixers this is how they get best quality mixer LO symmetry. Other methods include heavily filtering the signal (get it down to the fundamental sinusoid) and then run it through an AC coupled amplifier and get back up to the square wave. PLL and DLL methods work well also. Those are the methods that come to mind quickly. hope that helps, Jerry |
Title: Re: Clock Duty Cycle Correction Circuit Post by cirand on Oct 15th, 2006, 9:31pm i have ever designed a duty cycle correlation circuit based on the method of the attach paper. it is very simple and works well. |
Title: Re: Clock Duty Cycle Correction Circuit Post by ccd on Oct 17th, 2006, 11:31am Hi Cirand, I'm curious what you used for pulse generator in your duty cycle correction circuit as described in the attached paper. Thanks, ccd |
Title: Re: Clock Duty Cycle Correction Circuit Post by ywguo on Oct 19th, 2006, 7:32pm Hi, ccd, I am interested in the duty cycle correction circuit and read that paper. The PG can be implemented using some simple logic gates. BG Yawei |
Title: Re: Clock Duty Cycle Correction Circuit Post by neoflash on Nov 18th, 2006, 7:09am Thomas Lee had a paper on JSSCC on this, you can check with that. It is published in 2002, or 2000. |
Title: Re: Clock Duty Cycle Correction Circuit Post by cirand on Nov 23rd, 2006, 6:31pm ccd wrote on Oct 17th, 2006, 11:31am:
OUT= IN & ( #1 ~IN) |
Title: Re: Clock Duty Cycle Correction Circuit Post by jeffyan on Dec 21st, 2006, 3:54am ywguo wrote on Oct 19th, 2006, 7:32pm:
hi Yawei, the method proposed by the paper is too complex, i think there are three very simple ckt techniques you can find. one is proposed by j.maneatis. the sencond one given by LEE and KIM: "low-noise fast-lock Phase-locked loop" a jssc paper. the third one given by a.maxim in his paper "A Low-Jitter 125 ~ 1250 MHz Process Independent and Ripple Poleless 0.18μm CMOS PLL Based on a Sample-Reset Loop Filter". good luck jeff |
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