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Design >> Analog Design >> question about bootsrapped switch
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Message started by xaviar on Jul 22^nd, 2006, 6:45pm

Title: question about bootsrapped switch
Post by xaviar on Jul 22^nd, 2006, 6:45pm

My design requirement is SFDR>80dB.I had read some paper about it,most of them consider Vsb=/0 is the frist reason to distortion.My design implement not support triple-well technology,so choose pmos transistor is the only choice to me.Using pmos means more bigger W/L than the counterpart in order to achieve same Ron.
Firstly, large W/L have obvious feedthrough effect which is relate to Vin,it decrease the performance of switch.From the viewpoint of theory,bottom-plate sample can eliminate feedthrough and charge injection,but i use bottom-plate sample structure in Hspice, the result of simulation is that Vout is floating.How to configure the circuit to eliminate the feedthrough effect.
Futhermore, in order to compare the bulk-effect-free structure with bulk-effect structure,two structure is simulated by Hspice.The simulation indicate that bulk-effect-free structure decrease SFDR by 3dB,Why??
Last but no the least,what is the correct method to measure the performance of switch.I use Hspice to get *.tr0 and import the data to Matlab.It is found that TIME parameter is changing step,so it can't using period sampling.I have used a sine wave to test this method,some harmonic distortion (about - 60dB)and noise can be saw in the FFT plot-so confused! So mybe this method has fault,how to resolve it.

Thanks
xaviar

Title: Re: question about bootsrapped switch
Post by baohulu on Jul 22^nd, 2006, 10:52pm

Hi,
there is a paper related a method decreasing the clock feedthrough effect, "A 1.5V 50MHz pseudodifferential CMOS sample and hold circuit with low hold pedestal" IEEE. transactions on circuits and systems-I:regular papers vol.52,No.9,Sep.2005. I have tried this method, but I don't get a better result, I don't know whether there is something wrong with my design. however, hope this can indicate you something. and if you have got a better performance, please tell me.

I also have a question to ask you, in your opa, does it use a SC-CMFB, if yes, what is the type of the switch in your SC-CMFB, I use also the bootstrap type, but the charge injection and clock feed through is big , and this type can't make the CMFB stable to a VCM. I don't know what is type is suitable for the SC-CMFB.

xaviar wrote on Jul 22^nd, 2006, 6:45pm:

Title: Re: question about bootsrapped switch
Post by huber on Jul 23^rd, 2006, 10:37am

Hi xaviar,
The reason that a bootstrapped switch has lower distortion without the body effect is that Ron varries less. That said, I don't think the body effect should keep you from achieving 80dB SFDR, depending on your frequency and technology. I recently simulated a THA with +80dB SFDR at 60MHz input in 90nm CMOS; distortion from the bootstrapped input switches was very small, around the 90dB SFDR level.
About simulation: to measure distortion at this level, you wil have to force the simulator to take uniform time steps. In spectre this is done with the strobe command, but I don't know how it's done in HSpice.
-Dan

Title: Re: question about bootsrapped switch
Post by xaviar on Jul 24^th, 2006, 4:38am

Hi huber,
Thanks for your experience.I have tried to do FFT in Hspice,not import data to matlab,bootstrapped switch work great(SFDR>90dB).But this time switch always work in track mode,is it right?

baohulu,
I have used the structure you recommend,the result is same as you.Mybe the structure have reasonable in the theory,it should be noticed that dummy switch have parasitic capacitance.When the switch,which is connect Vout and dummy switch's gate, is opened ,the charge stored in Cs share with Cpara.It would decrease the performance.OPA's CMFB being design,i havn't enough experience to give you some advice,But the type of the switch in your SC-CMFB not need bootstrapped,because the switch have less requirement of distortion and it will consume more areas.Mybe the CMOS switch is right.