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Design >> RF Design >> pll synthesizer
https://designers-guide.org/forum/YaBB.pl?num=1153707949

Message started by dragonzj on Jul 23^rd, 2006, 7:25pm

Title: pll synthesizer
Post by dragonzj on Jul 23^rd, 2006, 7:25pm

As we know that the pll synthesizer has some main directive:the phase noise,the reference spurs,non harmonic spurs,the step size,reference phase noise,settling time....these directives affect each other.So when we optimize one,the other is deteriorated,for example,when we decrease the loop bandwidth,we can achieve good spur suppression,but it lead to the increase of the phase noise.So I hope that some one can give me more example of such cases so that I can sum them up.I think they would be very helpful when we designing our synthesizers.

Title: Re: pll synthesizer
Post by Eugene on Jul 24^th, 2006, 7:52am

I'm not sure I understand your question but I think I understand your problem. You must design a PLL to meet opposing performance requirements and design constraints. I have not seen a PLL design recipe that suits all PLLs. Perhaps that's why PLL designers have no trouble finding work these days. However, I can recommend an approach to the general design problem. In the absence of a reliable design recipe, I usually build AND VALIDATE a computationally efficient (i.e. fast) model of the system, along with simulation testbenches for all the performance metrics and design constraints of interest. Several CAE tools today have design optimizers. The models and testbenches bring these tools to bear on the design problem. In no way do I mean to imply that this approach is a "single stroke" solution. I always have to try several starting points and do several iterations to find a good solution. However, armed with the proper models and testbenches, the optimizers and parameter-sweeping tools let you explore the design space more quickly. Sometimes, I can prove that a solution does not exist. Such information is critical in negotiating specification relief.