The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> VHDL-AMS >> Delta delay in a procedure??
https://designers-guide.org/forum/YaBB.pl?num=1153998009

Message started by hskim on Jul 27^th, 2006, 4:00am

Title: Delta delay in a procedure??
Post by hskim on Jul 27^th, 2006, 4:00am

HI..
I am a VHDL beginer, some question..ㅠㅠ
doing the simulation..

If used signal assignment in a procedure(sequential subprogram), does delta delay apply to it(alike in a sequential process)??

If assign signal after delta time, when does signal assign?? Does it happen after procedrue finished(END)??