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Design >> Mixed-Signal Design >> Decision Feedback Equalizer- Stability analysis
https://designers-guide.org/forum/YaBB.pl?num=1154191705

Message started by sc123 on Jul 29^th, 2006, 9:48am

Title: Decision Feedback Equalizer- Stability analysis
Post by sc123 on Jul 29^th, 2006, 9:48am

I am implementing a decision feedback equalizer in CMOS. For high speed implmentation most DFE topologies I have found use clocked decision and delay blocks (digital) and the ISI cancellation is done in current mode (analog) at the input of the decision slicer. So it is a mixed signal approach. The DFE forms a negative feedback loop as the data decision signals control NMOS current switches that make the correction at the input of the decision slicer. I am interested to know if any sort of conventional ac stability analysis is required for such a topology. None of the papers I have looked at go into the conventional phase margin type of stability analysis. Is that because the circuit is not operating in the small signal regime? The clocked slicer and delay blocks will be high gain. So employing a high gain path in a feedback loop brings up stability issues and maintaining a closed loop phase margin less than 180 degrees is not feasible. However, transient simulations show good results and no signs of unstable behaviour ( undamped oscillations). What sort of stability analysis is required for a mixed signal DFE topology? Any thoughts or comments on this subject will be appreciated.

Title: Re: Decision Feedback Equalizer- Stability analysi
Post by loose-electron on Aug 3^rd, 2006, 3:39pm

Stability in a DFE system is non-linear in nature. As well, it is a sampled time system, so a conventional linear systems feedback system model is not applicable.

As well, the feedback amplitude is fixed in nature (make a decision and feed it back) so a "gain/phase around the loop" does not apply.

What is the DFE getting used for? I spent 2 years doing these things for disk drives and they do not work reliably. When you start adding in noise, signal input amplitude variance, timing dispersion, etc, etc, to the input signal, the DFE architecture starts to have a lot of problems. When you get that down into a chip and add process variance onto all of the above, it totally falls apart.

The concept is simple, and the math model looks good, but when you add the details of real world signals, and semiconductor limitations, there are a lot of problems.

Jerry

Title: Re: Decision Feedback Equalizer- Stability analysi
Post by sc123 on Aug 4^th, 2006, 5:47pm

Thanks Jerry. This confirmed what I had been thinking as well. I am looking at DFEs as part of my PhD research. DFEs are being looked at now to comabt ISI in multigigabit wired channels (backplanes, optical fiber). They were originally used in disk drives and now mixed signal topologies are being used to for high speed channel equalization. I can send you soem papers if you are interested.

Thanks, again

Soumya

Title: Re: Decision Feedback Equalizer- Stability analysi
Post by loose-electron on Aug 5^th, 2006, 1:23am

Lots and lots of academic papers got written on DFE for disk drives. To the best of my knowledge not one of them ever made it into a commercial product. The did work in tape drives, but not disks.

I am also aware of about 8 million dollars burned on (industry) research there. Amazing waste of money. :o

Backplane SerDes architectures? hmmmm, pre-emphais and post emphasis are needed if you are pushing the envelope, and I do know that DFE has worked there in papers published. If it is research, how about a pattern dependent pre-emphasis and a FFE Post emphasis architecture?

Other little nasty detail - model the backplane as a distributed, not a lumped, model. The responses are totally different and the distributed is more closely associated to reality.

Good luck with it!
:D
Jerry