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Design >> RF Design >> VCO + Divider phase noise simulation
https://designers-guide.org/forum/YaBB.pl?num=1154412060

Message started by ah_bhong on Jul 31^st, 2006, 11:00pm

Title: VCO + Divider phase noise simulation
Post by ah_bhong on Jul 31^st, 2006, 11:00pm

Hi,
I was simulating the phase noise of a VCO + Divider using PSS and PNOISE.
Two simulations were done and the two phase noise plot is taken,
one at the output of the VCO and one at the output of the Divider. (as attached below)
from the plot, the far out phase noise taken at the output of the VCO is extremely high,
while the phase noise taken at the output of the Divider looks fine.
Just want to ask, did anyone encounter such an incident before ?

Title: Re: VCO + Divider phase noise simulation
Post by ACWWong on Aug 1^st, 2006, 3:27pm

hi ah_bhong,

I'm pretty sure the error you have made is that you have incorrectly given the relative harmonic for the pnoise simulation.
As you have a VCO and a divide by 2, then the pss fundamental frequency is fvco/2.
So when doing the pnoise analysis at the VCO output, the relative harmonic for the pnoise is 2. You can confirm that this is correct by inspecting the spectre.out log and reading the bit at the start of the pnoise sweep. It should quote the vco frequency + relative sweep.
When repeating the simulation in the same testbench to inspect the divider output, you need to change the pnoise form to relative harmonic 1 (ie fvco/2), as well as defining the new output nodes. Again the spectre log will confirm now you are sweeping the noise centred at fvco/2 i.e. the divider output freq.

Once setup correctly, what you should see is the divider output phase noise should be 6dB lower than the VCO phase noise up until you reach the divider noise floor.

Cheers

aw