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Design >> Analog Design >> noise shaping of digital SD modulator in verilog-A
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Message started by mikev on Aug 1^st, 2006, 9:27am

Title: noise shaping of digital SD modulator in verilog-A
Post by mikev on Aug 1^st, 2006, 9:27am

I'm trying to understand the noise shaping of a digital sigma-delta modulator used in our PLL, so that I can use it in the linear noise anaysis. However, it doesn't seem to be acting the way I think it should.

The modulator we use is all digital. It dithers the LSB's of the N divider value. I don't understand how to model that using Ken's method in listing 8 of http://www.designers-guide.org/Analysis/PLLnoise.pdf . It technically has 0 DC noise (but the N-divider output does have noise, which I think should be modeled separately, since it isn't shaped by the modulator).

I have instead put a subtractor inbetween the VCO and N-divider. The VCO is on the positive input, and the moduator on the negative input, and the output goes to the N-divider. The moduator has the noise = 0dB at nyquist/2, and the slope of the noise is that of the order of the moduator. Does that sound correct?

Perhaps someone could give a good reference on modulators?

Thank you in advance.

Title: Re: noise shaping of digital SD modulator in veril
Post by Eugene on Aug 1^st, 2006, 1:44pm

I found the following paper very helpful in understanding and modeling sigma-delta modulator phase noise.

Michael Perrott, Mitchell Trott, Charles Sodini. "A Modeling Approach for S-D Fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis". IEEE Journal of Solid-State Circuits, Vol. 37, No. 8. August 2002.