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Modeling >> Semiconductor Devices >> mismatch modeling in simulation
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Message started by john_xu on Aug 1^st, 2006, 7:21pm

Title: mismatch modeling in simulation
Post by john_xu on Aug 1^st, 2006, 7:21pm

Hi,
We hope to do some mismach analysis when design our cicruit. But, unfortuntely, there is no mismatch parameter for our spice model.So I jsut vary the width 10~20% for the matched transistor. I know there is also the mismatch for the transistor lenght and the threshold voltage etc..But I just vary the transistor width.

Is there any risks when doing mismatch analysis for it?

Thanks

Title: Re: mismatch modeling in simulation
Post by Geoffrey_Coram on Aug 2^nd, 2006, 4:52am

If you vary the width, then the mismatch in current will be approximately linear, because the current goes to first order as W/L*beta*f(Vgs, Vds).

If you are operating in the linear region, then I guess this might be OK, since a variation in threshold voltage will also be linear. But then again, variation in length will cause an 1/x variation in current. And, if you are in subthreshold, you're completely toast, because a threshold voltage mismatch will cause an exponential mismatch in current.

Title: Re: mismatch modeling in simulation
Post by loose-electron on Aug 15^th, 2006, 9:16pm

What foundry process is this? and what channel length are you at?

The reason I ask - as you go under 90nm and the introduction of channles being shortened by "halo" methods and similar matching goes to garbage very quickly.

Consequently, playing with 20% channel geometry mismatch may not be enough.

Push back on the foundry really really hard for some matching data.

Jerry