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Design >> Analog Design >> OP AMP design
https://designers-guide.org/forum/YaBB.pl?num=1154525059

Message started by amitsingh on Aug 2^nd, 2006, 6:24am

Title: OP AMP design
Post by amitsingh on Aug 2^nd, 2006, 6:24am

Hi Guys,
I am starting a new topic for discussion inthis forum. So plz help me in sorting my queries.
PLease send me an Op amp design with specs and all the equations for a beginner to start design.
Thanks

Title: Re: OP AMP design
Post by ywguo on Aug 2^nd, 2006, 7:08pm

You need textbooks, tutorials, and so on. www.circuitsage.com is a good source for beginners.

If you have more specific questions, you will get more help at the designers guide forum. :)

Title: Re: OP AMP design
Post by amitsingh on Aug 2^nd, 2006, 10:31pm

Thanks for the link you gave to me. Actually i am doing Two stage Op amp. I have decided the W/L of two differential nMOS but i am struggling with W/L of Active current mirror load for my Op amp.Can you plz tell me how to decide the W/L of active mos load in current mirror configuration. Also it wold be good if you send me some thing regarding ICMR & OCMR.
Thanks

Title: Re: OP AMP design
Post by ywguo on Aug 2^nd, 2006, 11:08pm

You ought to decide the W/L of the active load that should meet the requirements of linearity, output swing, slew rate, gain, matching, noise, etc. Eventually it depends on your spec, maybe some are important, and something like noise could be omitted.

I remember Paul Gray had a paper on JSSC in 1970s. MOS OPAMP tutorial or something like that. :)

Title: Re: OP AMP design
Post by amitsingh on Aug 3^rd, 2006, 5:46am

Its great you are taking intrest in helping me.
Can you mail that link of Paul Gray.
I am working on 130nm process. I have specs like SR=20v/us, ICMR=.8,PM=60 deg, GM 70 db,UGB=80Mhz.
Plz send me the link from where i can find how to deal with all specs and decide parameters.
Thanks :)

Title: Re: OP AMP design
Post by jeffyan on Aug 3^rd, 2006, 6:05pm

i think you'd better go to read allen's book, very detail analysis to op-amp was performed.
the other thing is your process is .13,so some thing like short channel effects must be considered.
good luck. :o

Title: Re: OP AMP design
Post by ywguo on Aug 3^rd, 2006, 7:17pm

I am sorry that I made a mistake. That paper is named MOS operational amplifier design-a tutorial overview
by Paul Gray and Robert Meyer, JSSC, Volume 17, Issue 6, Dec 1982 Page(s):969 - 982 .

Title: Re: OP AMP design
Post by amitsingh on Aug 3^rd, 2006, 9:42pm

Thanks a lot i found the papers on IEEE site.
Its quite helpful. :D

Title: Re: OP AMP design
Post by amitsingh on Aug 8^th, 2006, 11:25pm

Hi
I am finished with my basic opamp design. My design has 75+db of gain, 56Mhz UGB and SR is 50v/us.
So now i want to characterize it, like CMRR, ICMR,PSRR,Offset and noise.
Please tell me how to achieve these values as per my spec.
Thanks

Title: Re: OP AMP design
Post by jbdavid on Aug 11^th, 2006, 2:45am

In Cadence Environment, I put together a rather basic tutorial on this, presented at the 2001 Cadence User Group.. Its now a white paper on the cadence website..
http://www.cadence.com/whitepapers/FVofDiffOpAmp_wp.pdf

The slides were presented at a couple of IEEE meetings and I found them (aint google great?)
at
http://engr.smu.edu/orgs/ssc/slides/20001215b.pdf

you might find them helpful..
Feel free to ask questions about the specifics here..

Jonathan

Title: Re: OP AMP design
Post by amitsingh on Aug 17^th, 2006, 6:37am

hi Jonathan
Thanks for the link you send to me.Actually i was out of town for quite sometime thats why i couldnt reply to you. I am getting following specs. You plz tell me how to improve PSRR? because the PSRR i calculated is degrading as the frequency of Operation goes into MHz range.

SPECIFICATIONS Obtained OPEN LOOP CLOSED LOOP
GAIN > 70 db 76db
GAIN BAND WIDTH >40MHZ 56MHZ 60 Mhz
PHASE MARGIN > 60 deg 60 deg 55 deg
ICMR >.8 v 1V
CMRR > 60 db 88db
SLEW RATE >20 V/us 36V/us
RANGE OF OPERATION 2 / 5 Mhz 2Mhz
Output Offset .00012V
Input Offset .00000395V
PSRR >80db 82db
Thanks

Title: Re: OP AMP design
Post by loose-electron on Aug 17^th, 2006, 11:03am

Your CMRR and PSRR will also go down as you introduce mismatch into the elements.

Start with either Monte Carlo (if you have statistical models) or do some small geometry mismatches and you will see them get worse.

The reason your PSRR is getting worse at higher frequencies is due (probably!) to the fact that capacitance coupling is more of an issue at higher frequencies and it is coupling through your PMOS active loads into the signal.

Also, don't forget to check PSRR with respect to ground noise as well.

Jerry