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Message started by aaron_do on Aug 2nd, 2006, 7:24am

Title: Phase Splitter..Receiver Architecture
Post by aaron_do on Aug 2nd, 2006, 7:24am

Hi all

just wondering is there any good reason why we should use a poly-phase splitter for the LO signal instead of the RF signal? Is it just a noise issue?

thanks
Aaron

Title: Re: Phase Splitter..Receiver Architecture
Post by ACWWong on Aug 2nd, 2006, 7:55am

You can use the poly-phase splitter to generate quadratutre LO, and I have worked on chips where we did that... but it seems to gone out-of-fashion to my mind because these days (with fast processes) its is now more common to use Master-Salve divide-by 2 to get the quadrature.
With the divide-by-2 you can get as good quadrature (phase & especailly amplitude) but for a wider input range of signals. With the polyphase, you need to align your casacaded stages (3 maximum to avoid excessive loss) to minimise amplitude ripple/mismatch... which if you have a large LO frequency range can be quite tough. Also there is no power penalty as the current you would have needed to drive the passive polyphase is now probably better imployed in a div2. div2 usually has a lower area penalty.

The polyphase is much better suited in reverse (combiner mode) in low-IF image reject archtectures, where the frequency range is now just the IF bandwidth.

I have never used polyphase splitter in the RF  before downconversion....

cheers
aw

Title: Re: Phase Splitter..Receiver Architecture
Post by aaron_do on Aug 2nd, 2006, 6:25pm

thanks for the reply

My main concern is current consumption.

I found that with a VCO and poly phase splitter i need a high power buffer in order to drive the upconversion and down-conversion mixer. That's why i was thinking of using a poly phase splitter after the LNA...then i can just bump up the power to my LNA. In this case i don't need to buffer quadrature LO signals, I can use a much lower power differential buffer.

I haven't considered the master-slave divide by 2 in the PLL. In this case i would need a 2f0 VCO and i would still need to buffer the divide by 2 right? Also in terms of power consumption is the master-slave divide by 2 better than a quadrature VCO?

thanks,
Aaron

Title: Re: Phase Splitter..Receiver Architecture
Post by ACWWong on Aug 3rd, 2006, 2:47am

whether 2*flo VCO & div2 is better than quadrature VCO (or flo VCO & phase splitter) depends on the frequency, and the nature of the proposed tank.

for example, if the BOM means off chip L is not acceptable, then the VCO power will be dependant on spiral L losses (Q~3 to 10 in CMOS/RFCMOS). so in this case a VCO running at 2GHz will probably be more power efficient and divide-by-2 might be better than a quadrture 1 GHz VCO (as L value needed at 2GHz is lower than 1GHz and Q is usually better for lower L values at higher frequencies). Even off chip L's only really give good Q's and usuable values @ > 500MHz
The situation at mid-GHz points (where Lreq is now only low nH or less) gives bondwires as attractive option, moving the tank Q bottle neck to varactor (Q>20), so i think a 4GHz VCO using bondwires to be better than a 2 Ghz using spiral L from the noise viewpoint, without power penalty.

the fact that 2*flo does mean the direct buffering is more power hungry, but i have found that current is better imployed in the VCO and div2 (ie no buffer required) given that the VCO has large swing and div2 is basically a digital circuit. the only reason a buffer would be required is for isolation, but when vco is at flo*2, this may not be a big issue on RX, and for loIF/ZeroIF fVCO≠flo is a must.

remember also the div2 gives a 6dB noise improvement to the VCO phase noise.

hope my comments give you some idea of some of the trade-offs, but basically i think you should play around with your design kit to deduce the best architecture for your receiver..

Title: Re: Phase Splitter..Receiver Architecture
Post by aaron_do on Aug 3rd, 2006, 6:49am

thanks for the help,

i'm not familiar with PLL design so i can't really tinker with it, but simulation seems to favor putting the poly-phase splitter in the RF signal path rather than the LO path. I just seem to recall reading a good reason why designers don't do it. By the way, why did you say for zero IF/low IF fvco≠flo is a must?

thanks,
Aaron

Title: Re: Phase Splitter..Receiver Architecture
Post by ACWWong on Aug 3rd, 2006, 8:48am


aaron_do wrote on Aug 3rd, 2006, 6:49am:
thanks for the help,

i'm not familiar with PLL design so i can't really tinker with it, but simulation seems to favor putting the poly-phase splitter in the RF signal path rather than the LO path. I just seem to recall reading a good reason why designers don't do it. By the way, why did you say for zero IF/low IF fvco≠flo is a must?

thanks,
Aaron


the VCO is usually quite powerful, as such its tone can usually be picked up all over a reciever chip (especially on bondwires and also via substarte, power supplies etc.). SO if you are trying to receive small signals on a snesitive LNA input or mixer input (at the same frequency as the VCO) you will find the signals you want will be swamped by the VCO leakage... this is the classic example of LO self mixing. being differential with good layout etc. helps but not enough in most cases....
So generally for ZIF and nearZIF (Very-low IF) one puts the VCO frequncy such that self-mixing products are out of the IF band.  i.e fVCO≠flo. The fVCO=2*flo and then divide-by-2 only suffers from self mixing across the mixer itself and the amount of flo power/devices switching at flo is much less so that in these cases its tolerable.



Title: Re: Phase Splitter..Receiver Architecture
Post by aaron_do on Aug 3rd, 2006, 8:57am

thanks for the advice!

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