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Design >> Analog Design >> Capacitor Matching
https://designers-guide.org/forum/YaBB.pl?num=1154954736

Message started by Faisal on Aug 7^th, 2006, 5:45am

Title: Capacitor Matching
Post by Faisal on Aug 7^th, 2006, 5:45am

Hi,

It is stated in different papers that the capacitor matching accuracy is of the order of 0.05 to 1 percent and its difficult to acheive a higher accuracy. On the other hand, my fab user manual states a formula through which I can acheive better matching accuracy than this number (theoretically) ?

I do understand that there are capacitor layout techniques (in our control) and some fabrication phenomenon (undercut, overetching etc).. But still I cannot find a reasonable explantion for this discrepancy ?

Title: Re: Capacitor Matching
Post by loose-electron on Aug 8^th, 2006, 2:24pm

Capacitor matching is pretty good on chips, but I would never ask for more that 1-2% - better than that and the architecture is too dependent on matching.

How many capacitors do you need to match?

A couple of pointers:

- Use a "unit cell" capacitor, all the same size and shape.
- Build your total capacitors out of paralllel arrays of these devices.
- Make the capacitors square to minimize perimeter length.
- Surround all caps with (exactly the same for all devices, using the same layers as the capacitor plates) perimeter ring.
- Ground out the perimeter ring.
- Make your unit cell capacitor 50% of the smallest capacitor needed. (That way you need 2 unit cells minimum in each full capacitor.)
- Interleave your unit cell capacitors. in a checkerboard pattern. (think common centroid layout concepts here.)
- Account for your metal interconnect parasitics carefully.

hopefully that should help some,
good luck with it,
Jerry

Title: Re: Capacitor Matching
Post by ACWWong on Aug 9^th, 2006, 1:48am

Faisal wrote on Aug 7^th, 2006, 5:45am:

I used a kit recently which according to the matching formulae provided for MIM matching, they can achieve 3 sigma match at 0.06% for a square 31umx31um (2fF/um^2 so 2pF) degrading to 0.2% for 10umx10um.
i'm was a bit sceptical of the formulae as it sounded a bit too good.... but maybe its becoming more true now in well controlled MIM fab steps. Tolerance is typically still at 10~15% for MIMs in most processes.

Anyway I would tend to agree with loose-electron, if you need much better than 1%, then your archtiecture is too demanding... The data of 0.2% 3 sigma quoted by the fab I was using did stipulate those results were obtained using the best matching layout practice across adjacent devices... over say a big switch-cap ADC where inevitably you use alot of caps over a large area, then the 1% rule of thumb is probably still useful, and will definately force you into designing a more robust circuit.

In addition to the notes provided by loose electron, i would add that you also need to be careful of automatic metal pattern fill or metal cheesing, which if not blocked by the user or manual implemented, can cause signficant mismatch MIM parasitic and hence MIM value. For more detail please see the related link to another post on this forum:
http://www.designers-guide.org/Forum/YaBB.pl?num=1146378302

cheers
aw

Title: Re: Capacitor Matching
Post by loose-electron on Aug 9^th, 2006, 12:22pm

AW -

Excellent point on the fill patterns. This especially is a bigger issue with copper, CMP methods, and the "persnickety" :D design rules to keep copper layers happy. Aluminum was a lot less fussy.

Three sigma at .06% ???
I will not drink that koolaid, no way.

What foundry claims this and on what processes?
Part of what I do is tear apart bad model situations, and running into these kinds of claims gives weight to the adage "don't beleive everything that you read, see or hear"

thanks,
Jerry

Title: Re: Capacitor Matching
Post by ACWWong on Aug 9^th, 2006, 5:20pm

loose-electron wrote on Aug 9^th, 2006, 12:22pm:

Three sigma at .06% ???
I will not drink that koolaid, no way.

What foundry claims this and on what processes?
Part of what I do is tear apart bad model situations, and running into these kinds of claims gives weight to the adage "don't beleive everything that you read, see or hear"

Yes, I didn't believe it either, and i spent a bit of time examining the formulae, looking for why i might be an order of magnitude out... i didn't find one of the usual classic mistakes like units or % instead of decimal. I did however notice the formulue had no input for dielectric uniformity, so i guess the mismatch values are reasonable when one only considers metal area mismatch... anyway i ignored the fab guide and i went back to my usual design method... the biggest unit cap i could get away with, without the parasitic being a problem... Faisal, I advise you to do the same unless your mismatch formula has covered all bases.

Anyway can't really quote the foundry, but its 0.13um CMOS MIM (nitride dielectric on M5).

cheers,
aw

Title: Re: Capacitor Matching
Post by Faisal on Aug 10^th, 2006, 9:08am

Thanks. for the replies.

Yes the application is demanding in the sense, that I would like to get the desired accuracy with minimal/without calibration/eror correciton.

I am using linear poly1-poly2capacitors (quoted as cpolylin) and the capcitor matching (sigma) = 1.3 % um / sqrt (W.L), so according to this formula even for a small capacitor lets say 10um * 10um, I should be getting 0.2 % capacitor matching. By making the capacitor area larger, this should get better theoretically (Also this is an analog process)

What I could glean from the literature is that there are two types of capcitor mismatches. The fab number is giving random mismatch and my layout quality will determine the systematic offset. Combined together this will determine the capacitor matching accuracy.

I am looking forward for comments

Title: Re: Capacitor Matching
Post by loose-electron on Aug 10^th, 2006, 11:32pm

Yes, I didn't believe it either, and i spent a bit of time examining the formulae, looking for why i might be an order of magnitude out...

Hm, ok, well, matching issus usually don't have a lot to do with easly dumped into equation type of thinking. Your "cautious pessimism" was a good thing.

Got to always question the foundry data, especially with digital centric foundries.

Jerry

Title: Re: Capacitor Matching
Post by ywguo on Aug 15^th, 2006, 8:09pm

Hi guys,

Metal pattern fill makes me headache. For some 0.13um process, it requires metal density from 15% to 82% in each 200um X 200um squares with 100um step from the origin. It is so difficult that designers cannot repair all metal density errors manually.

The first time I designed ADCs using 0.13um process, the foundry put many metal dummy in my chip, outside and inside my ADC. On that chip there are two similar ADCs. The measured results show that one is good, the other is bad. Until now I am not clear what's the reason. May I ignore the metal density errors and request not to fill metal patterns any more?

Thanks
Yawei

Title: Re: Capacitor Matching
Post by loose-electron on Aug 15^th, 2006, 8:40pm

With copper metal layers, you need to respect the physical design rules with respect to metal coverage.

This is due to the CMP processes associated with copper layers.
The interleaving of oxide and copper provides physical support during the CMP process.
When metal was Aluminum, it used to be a lot easier.

Suggest, do your own fill patterns layer by layer inside the block you are designing.

Jerry