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Design >> Mixed-Signal Design >> estimating jitter of on-chip buffers
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Message started by vivkr on Aug 8^th, 2006, 1:38am

Title: estimating jitter of on-chip buffers
Post by vivkr on Aug 8^th, 2006, 1:38am

Hi,

I want to know if there is any easy method to estimate the jitter introduced in a sampling clock by on-chip buffers. I want to use the clock in a high-precision, wideband sample-and-hold.

Normally, I would have preferred as little circuitry in the sampling clock path as possible, but a switched-capacitor circuit does need a few clock phases, and I need to generate these from my external clock without ruining the jitter performance.

How can I do this? I know that on-chip circuitry will typically add only small amounts of jitter but I would like to be able to check how much it does.

Any suggestions are welcome.

Regards
Vivek

Title: Re: estimating jitter of on-chip buffers
Post by loose-electron on Aug 9^th, 2006, 12:39pm

Vivek:

A possible approach to this would involve:

modeling the inherent noise of the buffer (thermal & flicker) - Come up with a time domain equivalent that can be summed with your signal.

add to that a time domain model of you interference noise coupling into the system

sum those two into your system, and run some multiple run simulations and generate the equivalent of an eye diagram.

Time jitter spreading will probably be heavily dependent on the dv/dt of the clock edges, with the noise superimposed on it.

I suspect that the inherent noise is not a big part of it

Annyhow, as a first stab, that is how I would approach it.
Good luck with it!

Jerry

Title: Re: estimating jitter of on-chip buffers
Post by smlogan on Aug 12^th, 2006, 7:43pm

Hi Vivek,

Another thought thay may (or may not!!) be useful to consider. I have been faced with a similar design situtation a number of times in the distribution of a reference clock to a SerDes. From measurements I've taken and the level of phase jitter I've been faced with meeting, the two dominant sources of signal integrity presented by the additional buffering are added deterministic jitter from the buffers (due to supply/ground noise) and the potential for differential skew. I'm not sure if your application uses a differential clock - hence the latter consideration may not be important to you.

For the case of added power supply or ground noise, many designers analyze this by modulating the supply or ground with either a single sinusoidal source or a broadband noise source and examine the resulting output phase jitter of the buffer. This can be accomplished through a series of transient simulations or harmonic balances simulations followed by a a noise analysis based on the harmonic balance solution.

However, a less computationally rigorous technique is to study the propagation delay through the buffer(s) of interest - from even a DC perspective. By examining the variation in the propagation delay of the buffer(s) as the supply voltage is changed, a direct measure of its variation with supplyvoltage is obtained. The resulting variation in prooagation delay will translate to phase jitter over the frequency range where the buffer can translate VDD-VSS variation to propagation delay - which is usually quite high in frequency. This can provide a direct indication of how sensitive the output jitter of a buffer - or series of buffers - is to noise on the supply or ground.

This technique can also be used to examine the amount of differential skew that will be imposed on a differential signal. Specifically if the variation in tpd (high->low) is different than the variation in tpd (low->high), then the skew will be a function of the amount of supply/ground modulation.

If this is not appealing to you, a series of transient simulations of the buffer(s) with different amaounts of differential input skew can be used to establish the robustness of the buffer(s) to the presence of differential input skew. As some differential buffers are designed to reduce input differential skew, this technque provides a direct indication of the degree to which differential input skew is attenuated.

I hope this is of some help!

Shawn

Title: Re: estimating jitter of on-chip buffers
Post by Ken Kundert on Aug 13^th, 2006, 6:04pm

You could use SpectreRF to predict the jitter. Just apply a representative large periodic input signal, and then perform a PNoise analysis configured to output jitter.

-Ken

Title: Re: estimating jitter of on-chip buffers
Post by loose-electron on Aug 14^th, 2006, 12:32pm

Ken:

PNoise and PSS are going to get you the inherent noise (shot thermal flicker) issues.

Thats great if it is perfectly quiet, nothing else running chip.
And - if the inherent noise modesl from the foundry are valid (IBM, TI, Jazz, ST, National all get this right)

But like I say in the prior post, I expect that the there will be more interference and switching noise issues. Those coupling paths are frequently not modeled until post LPE.

Jerry

Title: Re: estimating jitter of on-chip buffers
Post by ywguo on Aug 15^th, 2006, 7:25pm

All,

I agreed with Jerry. Though many papers and thesises contributed to the jitter analysis, I think the inherent noise due to thermal and fliker noise is not a big part. It is about hundreds of fs if there is only thermal noise. It is so small that it is impossible to be measured directly. I simulated and analyzed the thermal noise induced jitter several years ago using a method similar to Todd Weigandt. All papers and literatures I have read reports several ps to tens of ps rms jitter, which are one to two order larger than the thermal noise induced jitter.

BR
Yawei

Title: Re: estimating jitter of on-chip buffers
Post by loose-electron on Aug 15^th, 2006, 9:05pm

Yawei:

A good example of this is Ring Oscillator VCO's

The technique there is all about stabilizing the power, ground, substrate, and keep the transition switching in every " stage from "talking" to every other stage. Also, picking the number of delay stages such that they are fully and completly settled out before they start another state transition.

It becomes a careful exercise in layout, shielding, substrate contacts, local power regulation, and local high frequency decoupling.

The flicker/shot noise is a minor issue. The thermal noise even less so.

Jerry

Title: Re: estimating jitter of on-chip buffers
Post by Ken Kundert on Aug 16^th, 2006, 12:12am

For internal noise sources one uses a PNoise analysis, for external noise sources (such as coupling through the supplies or substrate) one uses PXF. As long as the interferreres are small, this works the best. It is both accurate and efficient.

-Ken

Title: Re: estimating jitter of on-chip buffers
Post by loose-electron on Aug 16^th, 2006, 3:10pm

Ken:

Got a web site on PXF I can take a look at?

Thanks,
Jerry

Title: Re: estimating jitter of on-chip buffers
Post by Ken Kundert on Aug 16^th, 2006, 11:26pm

Take a look at http://www.designers-guide.org/Analysis/rf-sim.pdf and search for PXF. It explains the analysis in general terms.

-Ken

Title: Re: estimating jitter of on-chip buffers
Post by Frank Wiedmann on Aug 16^th, 2006, 11:56pm

Note that for jitter, you need to use the Sampled PXF analysis, which is a pretty new feature of SpectreRF. In order to convert to jitter, you have to divide the result by the slope of the signal at the crossing point.