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Design >> Analog Design >> HCE(hot carrier effect) risk for my deisgn
https://designers-guide.org/forum/YaBB.pl?num=1155190295

Message started by john_xu on Aug 9^th, 2006, 11:11pm

Title: HCE(hot carrier effect) risk for my deisgn
Post by john_xu on Aug 9^th, 2006, 11:11pm

I am desiging a mixed signal block for which the output buffer is an inverter chains to drive the 1pF load capacitor. The design is based on the 0.5um CMOS.I use the minimum length for the inverter buffer with speed considerations.But I have some concern that the minimum length will bring the hot carrier effects which will affect the life of the product.

Pls. comment!

Title: Re: HCE(hot carrier effect) risk for my deisgn
Post by loose-electron on Aug 10^th, 2006, 11:36pm

What you are doing is done all over the place with many designs. It should not be a problem.