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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> What Killed Your Chip??? https://designers-guide.org/forum/YaBB.pl?num=1155585372 Message started by loose-electron on Aug 14th, 2006, 12:56pm |
Title: What Killed Your Chip??? Post by loose-electron on Aug 14th, 2006, 12:56pm Hey all - A new topic. This one is about what problems you have had. It is kind of a global question, because I am looking for additional topics to supplement a training course I do in this area. I already have a huge number of case studies - "you need to look out for this" stuff, but am always looking to add material. In my experience, the big problems with mixed signal chips reduce down to two major areas: -- Intereference noise due to analog-digital compatibility issues. -- Simulations that do not do the same thing as the silicon, due to a poorly defined model. So what problems have you had in your designs? A brief description of what the problem is/was and what you determined to be the issue would be much appreciated. [smiley=dankk2.gif] Jerry |
Title: Re: What Killed Your Chip??? Post by Andrew Beckett on Aug 20th, 2006, 3:29pm In my experience, most failures are due to failure to test (simulate) something in advance. For example:
And then there are design environment issues:
And this is to name just a few. Most errors tend to be human... I've seen a few which were due to model imperfections, but in practice those could have been spotted if the designers were being suitably paranoid. I always advise designers to question everything - if your design seems to be giving much better performance in simulation than you would have expected, ask yourself why, rather than just assuming it's because you're a brilliant designer! Regards, Andrew. |
Title: Re: What Killed Your Chip??? Post by loose-electron on Aug 21st, 2006, 1:22pm Andrew: A good post. I totally agree withy you with respect to the paranoia statement. ;D In my opinion, being a bit obsessisve-compulsive about all the fine details are what gets things to work the first time. I do see a lot of problems with mixed signal noise issues, and a number of problems with models, if people take the models and don't question them. Especially certain foudries produce inferior models and design kits. Also, if you are going out on a foudry with good models, your success rate is much improved. However, size of foundry and quality of models and PDK generally have nothing to do with each other. A lot of the noise problems occur when digital designers own the top end of the chip. My other favorite is when people decide to plug an RF front end into a mixed signal chip. Never say never, but I know of only 2 examples where people have gotten this working without problematic noise into the LNA. My take on that - get the design done with a dedicated LNA mixer chip first, and then if they insist on trying it, do it as a secondary path. Thanks for the feedback, I was begining to think that everyone had 100% perfect first time functional ships here. ;) Jerry |
Title: Re: What Killed Your Chip??? Post by ACWWong on Aug 21st, 2006, 3:15pm Its always the things you don;t check that catch you out.... when it gets to the top level of a chip there is often too much time pressure to meet a tape-out date, that you never do the simulations such as crosstalk/interference etc and just concentrate on the functional to ensure that you at least get something you can measure!! Unfortunately management are seldom obsessive compulsives, and don't like detail ! Having said that you can;t continue verifying and simulating forever, a balance needs to be struck... experience helps.... and so do risk reduction techniques like variants on the same MPW etc. Anyway I have been fortunate enough never to have taped-out silicon which didn;t function (i'll forget the time the fab missed out a poly mask!)... but have yet to meet full system performance on anychip which was any size first time. It has often been the case that the testchip cells stand alone performed to spec but the integration into a much bigger chips cause problems... exactly like the ones eluded to in the previous posts. |
Title: Re: What Killed Your Chip??? Post by jbdavid on Aug 29th, 2006, 12:01pm A good related question is "What ALMOST killed your chip.?" IE.. something NOT caught by a tool.. my list is fairly short.. Wrong order of bits between analog and digital interface out of ADC.. customer only needed 4 of 6 bits.. and almost got the low 4 bits.. Verilog-A Models simulated with digital was the only thing that caught this.. Not running simulations from the final schematic database.. Designer added a bit to a DAC, simulated it and fixed the layout, but forgot to copy the final schematic to the "real" database.. and was not around when the final LVS error showed up.. so we "fixed" the lvs error and his DAC has worse performance than before.. (since the two low bits are tied together!) Thus I discourage the practice of COPYING the design out to a development area, and encourage use of Design Management software.. and RE-running simulation AFTER check in.. Noise, electromigration.. Hope this helps.. jbd |
Title: Re: What Killed Your Chip??? Post by loose-electron on Aug 29th, 2006, 8:56pm Top level verification is still a big issue relative to methods used. There are some good methods and tools to get the job done, but often they don't get done, either people don't want to spend the money for the EDA, or people are stuck with legacy methods that don't fly with big chips. As for noise, I have spent a large amount of my time fixing noise problems in chips. I wish people would talk to me before taping out. That's one of the reason a large chunk of one of my training programs is all about analog-digital compatability and switching noise issues. |
Title: Re: What Killed Your Chip??? Post by jbdavid on Aug 30th, 2006, 12:00am You just gotta remember though, EVERYONE knows the right way to get the design done right. .. And they don't need to buy any more tools.. or hire any consultants.. until the chip comes back and doesn't work.. jbd |
Title: Re: What Killed Your Chip??? Post by sck236 on Aug 30th, 2006, 12:02am
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Title: Re: What Killed Your Chip??? Post by vivkr on Aug 30th, 2006, 3:41am # 1a Poor communication - Customer either has no real idea of how he wants to use the chip, or does not know which parameters are really critical and so leaves some unspecified, until he uses the chip in the app and then realizes #1b Poor system design - The above can also be counted as poor system design. In the end, the customer refuses to take the chip, and so effectively, the chip is dead even if it meets all your specs as specified. #2 Poor understanding of parameters: For instance, what exactly is meant by DC gain and how much do you need, and why? I have often heard people discuss how they need >120 dB DC gain, but only 70 dB settling accuracy will do. DC Gain means nothing, it is the accuracy to which the opamp inputs settle that counts. People learn this the hard way by measuring their chip results, and/or when they begin designing gain-boosted opamps and run head on into doublet-related settling issues :) #3 Muxing testmode pins onto analog pins without giving a thought to what might happen there in normal mode #4 Forgetting about the voltage range that a switched-cap circuit can handle. People forget about this, and get "mysterious" errors from charge-pumping action." #5 Poor layout: Despite the well-known fact that fully differential circuits are not fully differential unless you have made a perfectly matched layout, people go on laying things in strange and sometimes downright unacceptable configurations, and then see even-order distortion, noise problems etc. A lot of the problems can be classified as system-level issues. The list of such things could go on endlessly of course. Regards Vivek |
Title: Re: What Killed Your Chip??? Post by loose-electron on Aug 30th, 2006, 8:43am jbdavid wrote on Aug 30th, 2006, 12:00am:
"not invented here" and the human ego - I can not tell you the number of times I have seen those two issues cost organizations tens of millions of dollars... Correction - hundreds of millions... |
Title: Re: What Killed Your Chip??? Post by ywguo on Sep 6th, 2006, 2:18am First time I killed a chip, wrong connection at the top level. I had not simulated the whole chip because it needed too much time. I found the error when the chip was shipped back. Corrected with metal change. Second time I killed a chip, wrong change at the last minute. I changed the polarity of power down for one block at the last minute before tape out. I was so tired that I made a wrong dicision. I found the error before the chip was shipped back, and corrected using FIB. Best regards, Yawei |
Title: Re: What Killed Your Chip??? Post by loose-electron on Sep 7th, 2006, 11:23pm vivkr wrote on Aug 30th, 2006, 3:41am:
Vivek - A good list, the talk I have on simulation vs. silicon has almost 80 pages of "these things must be considered" - it is a long list, a lot based upon the "learning experiences" of a lot of designers. Jerry |
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