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Design Languages >> Verilog-AMS >> How to creat a loop filter model in VerilogA
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Message started by semitao on Aug 21^st, 2006, 6:48pm

Title: How to creat a loop filter model in VerilogA
Post by semitao on Aug 21^st, 2006, 6:48pm

Hi,
I want to creat a loop filter model in VerilogA. I found most loop filter model use R and C component, but I try to use the laplace function to describe this model, is that feasible?

Title: Re: How to creat a loop filter model in VerilogA
Post by ACWWong on Aug 22^nd, 2006, 4:02am

yes, laplace function should work fine... i think there used to be a "hidden state" problem with it in spectreRF simulations, but this has gone away now...

Title: Re: How to creat a loop filter model in VerilogA
Post by jbdavid on Aug 29^th, 2006, 11:25am

One of the problems I had with La-place is the fact that is immutable once setup..
IE you Can't change the transfer function during the transient simulation.. which is a problem if you
can switch capacitance or resistance in or out of the circuit to adjust for process, thermal, variation,
or to handle different types of inputs... maybe not generally the case for PLL loop filters, but thats
not the only place where this might be used. I once developed 32 parallel laplace functions and picked the one
selected by the control signal (a bus) but today I'd use a differntial model and change the coefficients based on the control signals..
ie

Code:

logic [4:0] BW_control;
electrical cap;
always @(BW_control) begin
C = cap_lsb * BW_control;
end
analog begin
I(cap) <+ C*ddt(V(cap));
end

of course you might want to change the capacitance nicely (transition) and get I(cap) to behave correctly on the transition, but
you get the idea..
Jbd