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Design >> Analog Design >> vco simulation
https://designers-guide.org/forum/YaBB.pl?num=1156230430

Message started by sugar on Aug 22^nd, 2006, 12:07am

Title: vco simulation
Post by sugar on Aug 22^nd, 2006, 12:07am

During transient simulation of a LC-VCO, I find some interesting phenomena.
At first, I use default setting of tran and my vco doesn't oscillate even for a long simulation time.
Then I set maxstep to 10ps (my vco's oscillating frequency is about 3GHz), this time it starts to oscillate.
I really cannot understand how it can start to oscillate.
I don't give any stimulus to the vco, so it should always stay at the balanced (although unstable) state.
Where does the 'noise' come from? from the accuracy of the simulator?

Title: Re: vco simulation
Post by loose-electron on Aug 22^nd, 2006, 7:56am

it's an oscillator, is it not supposed to oscillate?

By design, an oscillator is going to have enough gain and internal feedback (properly phased) to start oscillating.

As you say "but ustable" state.

Not sure I understand what the problem is.

Title: Re: vco simulation
Post by Ken Kundert on Aug 22^nd, 2006, 11:17am

There is a small amount of error in simulators that can trigger an oscillator. The simulator is working with finite tolerances, so the at the computed DC solution KCL will be violated by a very small amount. That error can be enough to start moving away from its unstable equilibrium point. However, if the transient analysis takes large time steps, it can quench the oscillation by adding artificial numerical damping (effectively lowering the Q). When you constrained the time step, you reduced the tendency of the simulator to quench the oscillation. Once the oscillation takes off, the simulator will naturally take smaller steps, keeping the oscillation alive.

-Ken

Title: Re: vco simulation
Post by sugar on Aug 22^nd, 2006, 7:10pm

thank you Ken,
that's what I wanted.