The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> Mixed signal simulation time
https://designers-guide.org/forum/YaBB.pl?num=1156247607

Message started by mady79 on Aug 22^nd, 2006, 4:53am

Title: Mixed signal simulation time
Post by mady79 on Aug 22^nd, 2006, 4:53am

I m working on mixed signal simulations with digital (rtl) and analog( ams ) .I appreciate if there are some ways to make the simulation faster by changing parameters like reltol ,time scale in AMS ..

My digital logic is small ,does wrting that digital in ams and having all ams models heps in simulation time ?? just curious ...
Thanks in advance ...

Title: Re: Mixed signal simulation time
Post by jbdavid on Aug 29^th, 2006, 11:13am

in Cadence you can use a profiler to see where the simulator is spending its time..
Generally speaking simulator time is
Behavioral < RTL < Gate,
but ALL of those are much faster than solving the analog circuit..

to get the most speed out of Verilog-AMS I look for places where the analog data is SAMPLED, or can be treated like a sampled system..
for those I use WREAL rather than electrical.. as this moves the signal out of the analog solver.
(my Tutorial from BMAS 4 years ago talks about this method a little and my paper from two years ago started the ideas in my head for
using logical signals on a differential signal pair.. which I expand on in this years paper.. (there is still time to register.. assuming your in the USA.. or can easily travel here..)

Its the Analog simulation that generally consumes the most resources so thats where you need to focus your modeling effort.
Jonathan

Title: Re: Mixed signal simulation time
Post by jbdavid on Sep 13^th, 2006, 10:44am

I try not to give too much advice here..
rather than "That's where you should focus your modeling efforts"
I meant rather to share my experience..
"That's where I tend to focus my modeling efforts"

jbd