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Design >> Analog Design >> Max VCO frequency in generic 0.13um process?
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Message started by bluestatic on Aug 28^th, 2006, 12:49am

Title: Max VCO frequency in generic 0.13um process?
Post by bluestatic on Aug 28^th, 2006, 12:49am

We are designing a VCO by using CMOS ring osc, trying to achieve minimum 3GHz for all the corners. The target process is S M I C 0.13um generic or S M I C 0.13um LV.
The VCO circuit itself, is a simple diff buffer than has both MOS and current source load.
When running at 0.13um LV process, the result is very good, the VCO can easily reach 3.3G even with full RC extraction. However, when we simulate the same circuit at 0.13um generic (1.2V), the result is really bad, it can hardly achieve 2.2GHz at post-layout stage. We tried to increase the tail current and also reduce output impedance of VCO circuit, it will improve a little, but still not as good the LV one.

I'm wondering if it is a process limitation that we can not reach 3.3G, or is there any other thing we can do to improve the VCO circuit's bandwidth?

really appreciate for any help.

Title: Re: Max VCO frequency in generic 0.13um process?
Post by loose-electron on Aug 28^th, 2006, 8:49am

Pushing the BW of a ring oscillator -

A suggested strategy - Use multiple phases off of the ring oscillator

for the sake of argument if a ring oscillator can run at 1MHx and you take signals off of 20 phases of a 20 delay stage system, you now have edge rates at 20MHz.

Way back at 0.5 um I did ring oscillators at 2GHz using this for a SerDes interface.

Title: Re: Max VCO frequency in generic 0.13um process?
Post by bluestatic on Aug 28^th, 2006, 10:06am

thanks for the reply, I'm not 100% sure if I got the idea correctly. Do you mean "Use multiple phases out of the ring oscillator?". 20 delay stages sounds quite a lot, which remind me about DLL design.

My current design is targeted on high speed but very low jitter, for time being there are only four delay cells in VCO and I took the output from one only. To me, more delay stage means more jiter due to varation of each delay cell, so the multiple phase solution might not work here.

The thing is, does 0.13um generic process has limited a single stage diff amp bandwidth to be less than 3G? Or it is just because I didn't do the circuit right?

thanks and regards

Title: Re: Max VCO frequency in generic 0.13um process?
Post by loose-electron on Aug 29^th, 2006, 9:52am

ON a TSMC 0.13 process I have done amplifiers up to 3.6GHz. (2X the high GSM band) but the capability to go a bit higher os there I beleive. People do 2.7GHz ISM band stuff all the time on 0.18

Now these are generally linear amplifiers, not switching devices (changing the current in the transistor vs. turning it on and off)

The multi phases off the ring oscillator is pretty straightforward - if you have a 4 delay ring running at 100 MHz, then if you take signals off of all 4 delays in the ring, then you have edge rates happening at 400MHz.