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Modeling >> Semiconductor Devices >> CV characteristic
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Message started by 337see733 on Aug 29^th, 2006, 12:54am

Title: CV characteristic
Post by 337see733 on Aug 29^th, 2006, 12:54am

Dear all,

I'm getting from Medici simulation result showing Cgb=Cbg. This puzzle me. These two capacitances should not be the same under any circumstances(except below threshold voltage), as they are related to different charges, the former is gate charge(or total charge) and the latter is bulk-charge, respectively.
Anyone have any experience to counter this problem? Thanks in advance.

Title: Re: CV characteristic
Post by loose-electron on Aug 29^th, 2006, 10:09am

Improper distribution of capacitance in a transistor model, not getting the depletion and bulk capacitnace effects modeled correctly is a very common problem in foundry models.

Sorry, that's the reality. What foundry model set is this? TSMC and UMC almost always mess this up.

Jerry

Title: Re: CV characteristic
Post by 337see733 on Aug 29^th, 2006, 6:04pm

loose-electron wrote on Aug 29^th, 2006, 10:09am:

It was a 2-D simulation results using Medici from Synopsys. Not really any model set in particular.

Title: Re: CV characteristic
Post by Geoffrey_Coram on Aug 30^th, 2006, 6:42am

For a moscap structure, I would indeed expect Cgb=Cbg; the gate charge must be equal and opposite the channel charge for charge neutrality.

Have you partitioned the channel charge into d, s, and b parts? Do you have Qd and Qs non-zero? In a MOS, if Qd=Qs=0, then Qb = -Qg, and it seems you're back in the moscap situation ...

Title: Re: CV characteristic
Post by 337see733 on Aug 31^st, 2006, 2:20am

Geoffrey_Coram wrote on Aug 30^th, 2006, 6:42am:

Yes, my model has non-zero qd and qs at strong inversion. However, my confusion is not with the model, but rather the simulation results shown in MEDICI simulation. Please find the attached. The Cbg is following Cgb, at Vds=0, which i suppose to be different from what i thought. Though Vds=0, i suppose it will still be different as there are still inversion charge at Vds=0 and some parasitic effects, such as the overlap charge should be added to the gate-charge. This device is very short, about 90nm(channel length), overlap length=20nm. It seems to me that the parasitic charges due to overlap is not included in the gate? or is it included somewhere else???