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Design >> Analog Design >> Power down simulation
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Message started by sck236 on Aug 29^th, 2006, 3:28am

Title: Power down simulation
Post by sck236 on Aug 29^th, 2006, 3:28am

In power down(shutdown) mode,

I want to see if the circuit has no floating nodes which might cause leakage current.

How can I do this simulation in spectre?

Just apply power down signal and watch the current out of the power supply?

If the current goes down near to zero, is it safe for leakage current?
and does it also mean there is no floating nodes?

In my opinion, even if there is no leakage current, there could be a floating node of which potential is zero.

I think this node may have leakage problem in a real circuit. Am I correct?

Thanks in advance.

Title: Re: Power down simulation
Post by ACWWong on Aug 29^th, 2006, 4:33am

Hi sck326,

Please see my comments/opinions, i hope they help:

sck236 wrote on Aug 29^th, 2006, 3:28am:

Yes, just applying the power down signals in a simulation should be fine. What is a tell tale sign of floating nodes, is the time it takes for the current to discharge to zero (or the DC value in power down) when one does a transient rather than DC simulation.

sck236 wrote on Aug 29^th, 2006, 3:28am:

If the current goes down near to zero, is it safe for leakage current?

Yes, assuming you have captured any non-schematic effects such as layout only devices like antenna diodes and alike.

sck236 wrote on Aug 29^th, 2006, 3:28am:

In my opinion, even if there is no leakage current, there could be a floating node of which potential is zero.

Agreed

sck236 wrote on Aug 29^th, 2006, 3:28am:

I think this node may have leakage problem in a real circuit. Am I correct?

Again if you capture all the layout devices, and have good models, you should NOT have a leakage problem.

cheers

aw

Title: Re: Power down simulation
Post by loose-electron on Aug 29^th, 2006, 9:43am

Power cycling, -- having been severely bit by this one ---

Suggest - simulating of power cycles often does not account for all the parasitic capacitances in the system, and a floating gate of a transistor is unpredictable in what it is going to do.

Suggest - If you are in PD mode, every single NMOS current source gate should be yanked to ground, and every single PMOS current source gate should be yanked to power rail. Also any and all current paths need to be defined as solidly switched off, using some form of a switch. No opening the circuit and letting it float down to ground as it discharges.

Been there, done that, gotten bitten, had to respin the chip.

Title: Re: Power down simulation
Post by uncle_ezra on Aug 29^th, 2006, 5:47pm

As a sanity check do a transient simulation with power supply going from high to low. This will most of the time give a different result than a simple DC analysis and it is also closer to reality.

Title: Re: Power down simulation
Post by sck236 on Aug 29^th, 2006, 11:40pm

loose-electron wrote on Aug 29^th, 2006, 9:43am:

Power cycling, -- having been severely bit by this one ---.

Suggest - simulating of power cycles often does not account for all the parasitic capacitances in the system, and a floating gate of a transistor is unpredictable in what it is going to do.

Suggest - If you are in PD mode, every single NMOS current source gate should be yanked to ground, and every single PMOS current source gate should be yanked to power rail. Also any and all current paths need to be defined as solidly switched off, using some form of a switch. No opening the circuit and letting it float down to ground as it discharges.

Been there, done that, gotten bitten, had to respin the chip.

What does "respin the chip" mean? ::)

Is there any rule of thub to determine the size of the switch which yanks the gate to ground or power rail?

Title: Re: Power down simulation
Post by loose-electron on Aug 30^th, 2006, 8:35am

Switch size? - generally min channel length, and some width that fits into your layout works.

As suggested above, doing some transient sims of power cyling is very valuable, power supply up-down, turning the PD control on-off at various times, having glitchy power on-off (switch contact bounce issues) will help you determine what is needed as part of power cycling.

Jerry

PS - respin = a "learning experience"

;D

Title: Re: Power down simulation
Post by uncle_ezra on Aug 30^th, 2006, 8:36pm

One more thing sometimes using minimum length can cause large leakage at some corners particularly if you are using core devices. So if at some corner the leakage is large try longer length device. I guess this is more pronounced for 0.18um and below.

Title: Re: Power down simulation
Post by loose-electron on Aug 31^st, 2006, 12:35pm

Leakage issues exist from about 0.35 and down. People did not start noticing them until they bacama a major issue (90nm? or thereabouts)

If leakage is a question, simulate at the hottest die temperature, where leakage is generally the worst.