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Design >> Mixed-Signal Design >> Analog power/area estimators
https://designers-guide.org/forum/YaBB.pl?num=1157132485

Message started by Visjnoe on Sep 1^st, 2006, 10:41am

Title: Analog power/area estimators
Post by Visjnoe on Sep 1^st, 2006, 10:41am

Hello,

I'm just interested how most of you do a area/power estimate of analog IP (prior to development, during prestudy), besides these approaches:

1. Deduce based on in-house IP
2. Deduce based on publications (papers)

In general, I believe it would be nice if there were more papers presenting power estimators for certain building blocks (e.g. pipelined ADC),
which correlate well with simulated/silicon results. There are a few, but a lot of building blocks are lacking.

Power/area is often the thing that potential customers are most interested in...

Kind Regards

Peter

Title: Re: Analog power/area estimators
Post by loose-electron on Sep 3^rd, 2006, 1:55pm

The problem here is that there are too many varaibles in the circuit architecture to be able to do this intelligently.

A lot of companies have attempted to automate analog design. All of them have failed.

Die size estimates on analog design are largely based on expereince, and knowing the typical architecture used for something.

Ditto on powere estimates, you need to know the architecture before you can do these.