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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> Analog Fault Model https://designers-guide.org/forum/YaBB.pl?num=1157607553 Message started by rahul_iitkgpvlsi on Sep 6th, 2006, 10:39pm |
Title: Analog Fault Model Post by rahul_iitkgpvlsi on Sep 6th, 2006, 10:39pm Hi, Could you please give me details idea about analog fault model? In DFT for digital system,there are few specific fault model.But for analog, I don't think there is any specific fault model.If you have any idea regarding this,please come up with your idea. Regards, Rahul |
Title: Re: Analog Fault Model Post by rf-design on Sep 8th, 2006, 12:36pm The fault models are similar. These are device orientied. Two terminal devices have opens and shorts. Three terminals have typical 2 shorts and three opens. The analysis bench is typical a netlist processing script which exchange one device by a faulty device model. Then the simulation result is compared to a test reference. If the fault could be observed the simulation test having coverage of this instance. |
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