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Design Languages >> Verilog-AMS >> IC analysis
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Message started by Venkateshr on Sep 7^th, 2006, 4:07am

Title: IC analysis
Post by Venkateshr on Sep 7^th, 2006, 4:07am

HI ,
Is there any way to find out the offset of any block say comparator or opamp(openloop ckt) in the ic analysis and then proceed on to use the offset in the tran.

I am doing dc sweep and writing the value to file and using that as ic for tran.

i tried one way oscillation by connecting two contradictory pins and the solution will be available only if the op of comparator turn high so then I get the offset.

Similar to inverter connected to itself thru an and gate whose select is another signal and selct has to be zero to have some settling point for the whole ckt.

Title: Re: IC analysis
Post by jbdavid on Sep 8^th, 2006, 12:55am

See my white paper on "Functional Verification of a differential operational amplifier" on the Cadence website.

it explains how to do this.

jbd