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Design >> Analog Design >> design of two stage operational amplifier
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Message started by avlsi on Sep 10^th, 2006, 8:28am

Title: design of two stage operational amplifier
Post by avlsi on Sep 10^th, 2006, 8:28am

Hi all,

I am designing a two stage opamp. My load capacitance is 25pF. My gain is 90 dB. Please help me in chosing
Tail current and second stage current in 0.18 u m process.

Slew rate is not important for me and my unity gain bandwidth is around 2 M Hz.

I am able to get 90 dB gain but my phase margin is 5 degrees.

Thanks in advance.

Title: Re: design of two stage operational amplifier
Post by Andrew Beckett on Sep 12^th, 2006, 1:12pm

This question is rather like "how long is my piece of string".

There are plenty of books which cover op-amp design well (see the Books link at the top of the page).

It's not just a matter of choosing the currents - your compensation needs to be correct too. There are too many variables to infer what the right thing to do is from your rather limited description.

Andrew.

Title: Re: design of two stage operational amplifier
Post by avlsi on Sep 12^th, 2006, 7:35pm

Is there any book that really teaches design?

Most of them theory, and even if they teach ,not short for short channel design.

May be you can send me some links for the books.

Title: Re: design of two stage operational amplifier
Post by jbdavid on Sep 13^th, 2006, 12:06am

If design that just applied pre-existing rules reliably produced innovative results we could write software programs to apply those rules and generate the designs.

Innovation requires understanding of what has been done before.. (that pesky theory you complain about) and a little creativity.

At least one design teacher I know thinks that the most successful approach is to simply throw the students at the problem... once they have the basic theory. If they are able to make the intellectual leap to becoming designers they pass. Maybe even if they just get close..

so spend a little time to master the theory, then jump in and start designing.. analyze it, and start improving it..
at some point you'll get the hang of it.. or go into CAD..
Jonathan - I STILL don't want to be a CAD guy..
;)

Title: Re: design of two stage operational amplifier
Post by avlsi on Sep 13^th, 2006, 12:44am

Hi,

Thanks for your constructive criticism. I am going thru the theory.

I am not expecting a spoon fed technique to design an opamp. I am just trying to know,how people can optimise their designs.

I think its from experience.

I am trying to get that. In this process,I want to know how others do?

Title: Re: design of two stage operational amplifier
Post by vivkr on Sep 13^th, 2006, 5:03am

Hi,

As already pointed out in the previous replies, you need to figure out how to use concepts from theory and apply them successfully to design. There are three things I would like to recommend:

1. Understand what controls what, even for parameters that are not important for you lest your design makes them critical. e.g. What restriction do you have for the minimum compensation cap?

2. Avoid making lazy choices for critical components e.g. Cc=1 pF is so widely used by designers, often when a much smaller cap would suffice.

3. When compensating a two-stage opamp, avoid the temptation of compensating by increasing Cc aggressively. Instead, focus on increasing Gm of the second stage. It helps much more (the theory will tell you why).

A very good introduction to designing two-stage amps is provided in some tutorial lectures by Dr. Willy Sansen. I imagine that similar material may be found in Laker and Sansen, or on the web.

Regards
Vivek

Title: Re: design of two stage operational amplifier
Post by avlsi on Sep 13^th, 2006, 7:13pm

Hi

Your reply seems interesting.

I have thought to use an optimum Cc. I am using now 5p F.I want to restrict myself to that,since it affects my area and noise.

I calculate the affect of pole and zero at second stage.

Second stage gm = 10 * first stage input gm.

This will affect my current consumption.

I have been seeing many people,who just think analog is like a trial and error procedure. They know the theory but really cannot tell you ,why they took this value.

I feel for any specification,there is an optimum circuit.

I am going through willy sansen and Kenneth. R. Laker book about design of two stage OTA.

Can u tell how can we plot a graph like this - Log(Av) Vs Log(Ids)

I want to do this to find optimum value of tail current.

I know wht is the best L I can use to get some specifiec gain. I plotted gain for different L.

Thanks in advance

Title: Re: design of two stage operational amplifier
Post by vivkr on Sep 14^th, 2006, 1:15am

avlsi wrote on Sep 13^th, 2006, 7:13pm:

Hi

I have thought to use an optimum Cc. I am using now 5p F.I want to restrict myself to that,since it affects my area and noise.

Good to see that you choose the Cc based on noise.

Quote:

I calculate the affect of pole and zero at second stage.

Second stage gm = 10 * first stage input gm.

This will affect my current consumption.

You should also take a look at the paper by Ahuja (JSSC, Dec. 83 I think). Since you mention that slew rate is not important to you (and I hope you have investigated this well), you can use this scheme. There are 2 drawbacks of this scheme:

1. An extra stage is added => more current, especially is slew rate matters (not in your case)

2. Systematic offset introduced as two current sources fight each other in the intermediate stage.

However, it should allow you to improve the stability of your opamp quite a bit for lower current and will also give a better opamp. If you are making a fully differential design, then the systematic offset issue may not be as severe. The big advantage here is the elimination of the RHP zero.

Quote:

I have been seeing many people,who just think analog is like a trial and error procedure. They know the theory but really cannot tell you ,why they took this value.

A pity! How the pioneers would cringe. Let us remember that a couple of decades ago, there was only one kind of circuit design, and people would have laughed if you told them that this sort of design (now analog) could not be done systematically and optimally, even if it was not possible to automate it.

Quote:

Can u tell how can we plot a graph like this - Log(Av) Vs Log(Ids)

I want to do this to find optimum value of tail current.

I know wht is the best L I can use to get some specifiec gain. I plotted gain for different L.

Thanks in advance

Depending on the tool you use, you can usually just switch axes to log scale, e.g. Spectre allows plotting of gain in dB, and if I remember well, so does HSPICE.

Just a word of caution, if you sweep L or any other device parameter using an automated sweep, you may get incorrect results. I have not done this for a while, but the last time I did it, the results were wrong because tools don't handle the model binning correctly when you sweep a device parameter, and surely, things like source/drain diffusion parasitics are not correctly scaled. So, you should physically change the device properties, re-netlist, and run simulations, or else create two separate devices with different L, and simulate them in parallel as separate instances.

Regards
Vivek

Title: Re: design of two stage operational amplifier
Post by avlsi on Sep 14^th, 2006, 7:47pm

Thanks for your suggestions Vivek, I am designing a single ended ouput amplifier.

Title: Re: design of two stage operational amplifier
Post by nobody on Sep 17^th, 2006, 1:00am

vivkr wrote on Sep 13^th, 2006, 5:03am:

2.
The valuse of Cc basically depends on this "fnd=3GBW" to have phase margin of 70.
Cc/CL=K*(gm1/gm2) where gm1 represents the input stage gm and gm2 is the 2nd
input gm. I do not understand why Cc will have an effect on noise. All i know is about
the input referred noise. Increase 1st stage of gm will reduce the input referred noise.

3.
Hi,Vivkr. To increase the gm of the 2nd stage will increase the system offset.
Is that right ?
4.
Can you kindly post the link which has the tutorial you mentioned ?

Title: Re: design of two stage operational amplifier
Post by vivkr on Sep 19^th, 2006, 7:37am

nobody wrote on Sep 17^th, 2006, 1:00am:

vivkr wrote on Sep 13^th, 2006, 5:03am:

Hi,

2.
The valuse of Cc basically depends on this "fnd=3GBW" to have phase margin of 70.
Cc/CL=K*(gm1/gm2) where gm1 represents the input stage gm and gm2 is the 2nd
input gm. I do not understand why Cc will have an effect on noise. All i know is about
the input referred noise. Increase 1st stage of gm will reduce the input referred noise.

It is correct that the increasing Gm1 will reduce the noise power spectral density (input-referred). However, for a given Cc, increasing Gm1 will also widen the bandwidth => noise bandwidth of opamp increases. If you assume a first order opamp as the limiting case, then the reduction in the input noise PSD is exactly offset by the increase in bandwidth resulting in a total noise (integrated over whole bandwidth) which is independent of Gm, but only depends on Cc and temperature. If the opamp is the dominant noise source and is also the component limiting the system bandwidth, then you will always have to increase Cc to reduce total noise.

Quote:

3.
Hi,Vivkr. To increase the gm of the 2nd stage will increase the system offset.
Is that right ?

The question is not clear to me as I am not sure if you are referring to the standard 2-stage opamp or the Ahuja-compensated opamp, and if the latter, then which stage you would call the second. Just briefly, I don't think that a higher Gm2 would increase systematic offset in the standard design or in the Ahuja design as long as the currents are ratioed correctly. However, the presence of the intermediate stage in the Ahuja compensation scheme (see paper) has a current source of its own tied to the output of the first stage. As the two current sources will tend to fight, the result will be a systematic offset in a single-ended design.

[quote]

4.
Can you kindly post the link which has the tutorial you mentioned ?

I did not say that I have a link to this tutorial. Only that you may find it on the internet (perhaps).

Regards
Vivek

Title: Re: design of two stage operational amplifier
Post by yora on Sep 28^th, 2006, 1:55am

Hi, I have a question of the system offset.
What else except mismatch would cause an offset?
Why the 2 current source would cause a system offset?
And I am doing a differential amp, but it still has an offset though I haven't include any mismatch in the simulation.
I think it is very strange. Cause though there is no DC offset, the transient output has different Vpeak in positive and negative sides.
What could be the reasons?
Thanks!