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Design >> Mixed-Signal Design >> the peak di/dt issue in dsign phase
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Message started by john_xu on Sep 10^th, 2006, 6:48pm

Title: the peak di/dt issue in dsign phase
Post by john_xu on Sep 10^th, 2006, 6:48pm

Hi,
For my TTL/CMOS buffer design, i found the peak di/dt is high up to ~500MA/s in simulation. Here MA is mega ampere. I know,it will cause the serious vdd/gnd bounce.But we know, in actual conditions, it is not so pessimistic.Many solutions will be used to improve it, e.g, the bypass cap in PCB bord.

I want to know, is 500MA/s current change rate be tolerable in simulation phase?
Will it cause any EMI concern?

Can anyone shed some light on it?

Thanks

Title: Re: the peak di/dt issue in dsign phase
Post by loose-electron on Sep 11^th, 2006, 10:20pm

You might want to start including some of the parasitic RLC elements. It sounds like you may have some ideal elements that are giving you some misleading results.