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Design >> Analog Design >> stability of SHA SC ckt (Pipelined ADC)
https://designers-guide.org/forum/YaBB.pl?num=1158386140

Message started by packiaraj on Sep 15^th, 2006, 10:55pm

Title: stability of SHA SC ckt (Pipelined ADC)
Post by packiaraj on Sep 15^th, 2006, 10:55pm

Hi forum,
A doubt, How do we ensure that the OTA is stable when in sampling mode? For Ex. The OTA in Flip around SHA SC ckt would see the load in sampling mode different from that in hold or amplifying mode (In amplifying mode SHA is loaded by the first stage MDAC capacitors). Naturally, we decide the OTA UGB and Gain based on the tolerable final settling error and finite gain error specifications. So here we take into account only the capacitive load in amplifying mode. But OTA designed, in place, would see a less load in sampling mode, so UGB changes, but to my eyes the non-dominant poles does not seem to move atleast for the first degree...hence PM changes... So a great threat to the stability??? Any help that makes me understand this will be greatly appreciated!!!

Thanks,
Packiaraj.V.