The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> power losses https://designers-guide.org/forum/YaBB.pl?num=1158438238 Message started by grosser on Sep 16th, 2006, 1:23pm

Title: power losses Post by grosser on Sep 16th, 2006, 1:23pm hello can you tell me what are the main causes ofpower losses in submicron technologies? and what are the ways to reduce it? the second thing is what are the rules of drawing clock in the layout to avoid delays and distortions? regards

Title: Re: power losses Post by ACWWong on Sep 20th, 2006, 5:18am grosser wrote on Sep 16th, 2006, 1:23pm: hello can you tell me what are the main causes ofpower losses in submicron technologies? and what are the ways to reduce it? the second thing is what are the rules of drawing clock in the layout to avoid delays and distortions? regards hmm.... power losses... well i guess you mean digital circuits so, for deep submicron technologies leakage (gates that are not switching/gates that are off) is a problem. Ways to address it are to use stacked device logic cells rather than standard cells... clock tree routing and buffering insures clock skew (delays/distortions) are kept to a minimum. I believe this is a standard thing that most digital synthesis tools can do for you if you give it the constraints. cheers aw

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