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Design >> RF Design >> How to reduce prescalar noise?
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Message started by ezbentley on Sep 25^th, 2006, 11:16am

Title: How to reduce prescalar noise?
Post by ezbentley on Sep 25^th, 2006, 11:16am

What are some techniques to reduce the noise contributed by the frequency divider? I heard one way is "re-timing." How does it mean?

Title: Re: How to reduce prescalar noise?
Post by rf-design on Sep 26^th, 2006, 12:59pm

If you use an asynchronuous divider the phase jitter of the individula stages accumulate. Typical in CML there is also current scaling for the stages operating at lower frequencies. These contribute more to the output jitter of the critical edge. A way to avoid this accumulation is to use a noise optimized register to resynchronize the last noisy edge with the input clock.

Be careful with delay issues! If the noisy edge to synchronize is in the critical register window you can have undefined output states.