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Design >> RF Design >> About CMOS power amplifier design
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Message started by cedar on Sep 26^th, 2006, 8:31pm

Title: About CMOS power amplifier design
Post by cedar on Sep 26^th, 2006, 8:31pm

Hi,

I have a few questions about CMOS power amplifier design. The first one is S22. Is it important to have a good S22( good means S22<-10dB) and how to achieve it? When I was designing a class-A PA, first I will define the transistor size based on the output power, and then found the optimum load impedance using load-pull method. The third step is to match the input impedance. Next it is to match the output impedance from 50 Ohm to the optimum load impedance for maximum output power, but S22 may be bad. So how do we compromise between maximum output power and S22?

My sencond question is temperature compensation. From simulation, I found that the power gain varies a lot over temperature. Is there any good method to overcome it? I am thinking of adding gain control over temperature but this may cause matching difficult.

My third question is about bonding wire model. Do we need to put the exact bonding wire model in the simulation or just give an estimation of inductance and resistance?

My 4th question is about stability. If the stability factor is satisfied, but there is still oscillation. How can we simulate and verify it?

thank you for your input,

cedar

Title: Re: About CMOS power amplifier design
Post by ACWWong on Sep 27^th, 2006, 4:20am

Hi cedar,
my 1p's worth would be:
1) The compromise between of maximum power with S22 shouldn't be such an issue, as the max power will generally coincident with good S22.
2) Bias control/design is often used to compensate temeprature gain variation. Either open loop (just give the bias an appropriate temp coeffiecent) or closed loop (sniff power, compare in control loop to control bias).
3) The more exact the modelling of the pads, bondwire, package, PCB the better!! Just using L and R without appropriate C will be problematic for the accuraccy of your simulation.
4) Potential oscillation may occur if you have not modelled all the coupling mechanisms which are not present in a simple schematic simulation. Layout coupling (capacitive and also inductive) both on the die, via bondwires, package and PCB can often cause unexpected oscillation. Careful attention to these points should allow you to predict/address potential oscillation problems.
cheers
aw

Title: Re: About CMOS power amplifier design
Post by cedar on Sep 28^th, 2006, 12:47am

Wong, thank you for the answer. But it looks too general and there are many limitations in the actual design.