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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> about 1.5 bit https://designers-guide.org/forum/YaBB.pl?num=1159473222 Message started by blackbird on Sep 28th, 2006, 12:53pm |
Title: about 1.5 bit Post by blackbird on Sep 28th, 2006, 12:53pm 1.5 bit +-1/4Vref confused me.....why was that? :-[ can anyone tell me the detail or reference about it ? |
Title: Re: about 1.5 bit Post by Faisal on Sep 29th, 2006, 8:17am 1.5b and 1/4 Vref refers to ADC static characteristics. Almost all the pipelined/cyclic ADC have some redundancy and can be 1.5b, 2.5b or higher (for accomodating comparator offsets). Pick any good book/thesis on ADC and you should get a starting point. ;) |
Title: Re: about 1.5 bit Post by blackbird on Sep 29th, 2006, 8:12pm yes,I definetly read some papers about pipelined ADC...but I still don't know why.... Why do we need to shift precision levels 1/4 Vref to the right from the 2 bits per stage architecture ? |
Title: Re: about 1.5 bit Post by jbdavid on Sep 30th, 2006, 1:14am What do you mean "to the right"? This is probably not easily described in a few words.. I used a diagram on page 14 of my bmas2002 tutorial that helped me describe it.. but I kept few details in it.. http://www.bmas-conf.org/2002/papers/bmas02-david.pdf basically the x-axis is a single stage input range.. (-Vmax -> +Vmax) and the y-axis is the stage output residue.. so the slope is the gain of the stage and the discontinuities show where the comparators switch state. I found this to be the best tool to get my mind around the design.. Hope it helps you too. jbd |
Title: Re: about 1.5 bit Post by blackbird on Sep 30th, 2006, 6:51am thank you for your help, first of all. "to the right" means the decision-level of x-axis on 1/4 Vref which comes from a paper named A 10-b 20-Msample / s Analog-to-Digital Converter ,writen by Stephen H. Lewis, IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 27. NO. 3. MARCH 1992. |
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