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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> model of capacitor, controlled with voltage need https://designers-guide.org/forum/YaBB.pl?num=1160140407 Message started by stary on Oct 6th, 2006, 6:13am |
Title: model of capacitor, controlled with voltage need Post by stary on Oct 6th, 2006, 6:13am Gurus, please, help me! I want to use a voltage-controlled capacitor of type: c = c0 + k*V(vc1, vc2) here c0 and k are constants; vc1, vc2 - controlling nodes. So I try to describe it as: I(vp,vn) <+ ddt( (c0 + k*V(vc1, vc2)) * V(vp,vn)); // (vp and vn are own nodes of capacitor) But the compiler puts an error (rather long message). The main reason, as I understood, is mix of controlling and own voltages in one exepression. How it can be written in other form? |
Title: Re: model of capacitor, controlled with voltage ne Post by Ken Kundert on Oct 6th, 2006, 10:30am If you are asking us to interpret an error message for you, it is helpful if you include the message in your post. Even better would be to include your model and perhaps a test circuit that exhibits the problem as well. Have you taken a look at http://www.designers-guide.org/Modeling/varactors.pdf? -Ken |
Title: Re: model of capacitor, controlled with voltage ne Post by stary on Oct 8th, 2006, 10:54pm Hi, Ken I want to simulate a capacitor, linearly controlled with a voltage: c = c0 + k*V(vc1,vc2) here: c0 - initial capacitance, k - a constant vc1, vc2 - the controlling nodes of capacitor and this capacitor placed between nodes vp and vn. According to your paper I changed model of this capacitor on: I(vp,vn) <+ ddt(c*V(vp,vn)+k*V(vc1,vc2)*V(vp,vn)*V(vp,vn)*0.5) (i.e., I(vp,vn) is calculated via charge-based model.) Again I get an compiler' error: dynamic quantities must be linearity accessible. What is the reason of error and how it can be fixed? |
Title: Re: model of capacitor, controlled with voltage ne Post by Ken Kundert on Oct 8th, 2006, 11:38pm I don't know. Your model seems fine to me. What does your vendor say? -Ken |
Title: Re: model of capacitor, controlled with voltage ne Post by stary on Oct 9th, 2006, 12:29am Oh, Ken, you don't sleep?! Unfortunately, no access to vendor. If it can help, the full text of model is: `include "discipline.h" `include "constants.h" model cap1 (vp, vn, vc1, vc2); inout vp, vn; input vc1, vc2; electrical vp, vn, vc1, vc2; parameter real c = 0; parameter real k = 0; analog I(vp,vn) <+ ddt (c*V(vp, vn) + k*V(vc1, vc2)**V(vp, vn)*V(vp, vn)*0.5); endmodule |
Title: Re: model of capacitor, controlled with voltage ne Post by Geoffrey_Coram on Oct 9th, 2006, 6:09am stary wrote on Oct 9th, 2006, 12:29am:
s/model/module ? Quote:
Did you intend the ** in there? My compiler has no problem with the module. |
Title: Re: model of capacitor, controlled with voltage ne Post by stary on Oct 9th, 2006, 6:21am Yes, I did mistake when typing this text here, valid line is: I(vp,vn) <+ ddt (c*V(vp, vn) + k*V(vc1, vc2)*V(vp, vn)*V(vp, vn)*0.5); Version of software is: Virtuoso 5.1041_USR3.27.30 I cannot say exactly - s/model/module. It is a model of one of circuit's block. |
Title: Re: model of capacitor, controlled with voltage ne Post by Ken Kundert on Oct 9th, 2006, 8:06am This appears to be a bug in the simulator. I was able to work around it by assigning the argument of ddt() to a local variable, and then applying ddt() to that variable. So in particular, I used Code:
-Ken |
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