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Design >> Analog Design >> Simulation of voltage offset of the comparator
https://designers-guide.org/forum/YaBB.pl?num=1160509697

Message started by bharat on Oct 10^th, 2006, 12:48pm

Title: Simulation of voltage offset of the comparator
Post by bharat on Oct 10^th, 2006, 12:48pm

In my comparator design, the spec for bandwidth is very high or the absolute delay from datain to dataout is very less. To acheieve this I ended up using minimum channel length of the devices. Now running the dc sweep simulation for offset I am getting very low offset value. and running statistical tool for offset and looking its 3sigma value is well within the specs and it hard to believe on the results.
Now my concern is: is there simulation to silicon mismatch OR the process is still not matured? because text book (common theory) says that lesser channel length will result higher offset.

Also, apart from DC sweep method of calculatiing offset, what if I give one of the input as Vref (reference voltage) and the other one as very slow rising/falling signal (say 1v/ms) and see how the output is toggling in transient response? Hence calculate the offset. Whether this method is more accurate? If so, why?

-Bharat

Title: Re: Simulation of voltage offset of the comparator
Post by SATurn on Oct 10^th, 2006, 1:10pm

Regarding to statistical simulations; please remind that tool considers the total transistor area (not just the transistor length) to estimate the statistical parameters. Must probably the area of your device is quite large. Of course, it is important also that if you have splitted the proposed deivces to smaller ones or not. I would suggest to check the process documentation to investigate how it is exactly modeled.

I think also "DC sweep + MonteCarlo" would be quite accurate for this purpose and you don't need to run the "time consuming" transient simulations.

Title: Re: Simulation of voltage offset of the comparator
Post by hunk on Oct 10^th, 2006, 11:40pm

it is true for "less device, less mismatch". consider the layout and tapeout if using less dimension device the comp will suffer from matching-problem. there is tradeoff between speed and offset.

regarding of offset simulation the dc and slow tran sweep will get the same results. but the tran must be very very slow. basically the dc is the first choice.

Title: Re: Simulation of voltage offset of the comparator
Post by loose-electron on Oct 11^th, 2006, 10:40pm

What foundry and foundry process is this on?

Also, get from the foundry the lab data taken from silicon to determine the mismatch of the devices.

Foundry models can have a lot of problems in accuracy here.