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Design >> Analog Design >> What is the effect of ICMR
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Message started by chviswanadh on Oct 11^th, 2006, 4:06am

Title: What is the effect of ICMR
Post by chviswanadh on Oct 11^th, 2006, 4:06am

Hello,

I couldnt understand the effect of ICMR on operational amplifiers performance.

I can understand that opamp input should lie in the ICMR range for proper operation but what happens if the input is out of ICMR

whether the gain is 0 or the output is clipped or there is an distortion in output.

Please give some inputs on this

Thanks
chviswanadh

Title: Re: What is the effect of ICMR
Post by ACWWong on Oct 11^th, 2006, 4:51am

The input common-mode range must be adhered to to ensure the input devices of the operational amplifier are operating correctly.
For example an N device input op amp will have reduced/no gain if the ICM signal is too low (because the input devices become off) and if the ICM is too high it might also give reduced gain/distortion due to headroom issues (triode for MOS, Saturation for BJT).
Similar complementary problems might exist for P inputs, so the ICMR must be adhered as quoted on the opamp datasheet.
Large ICMR is achieved in "rail-to-rail" opamps (which use complementary N and P inputs). Even in these designs, you must look carefully at what "rail to rail" actually means in terms of performance of the opamp.

cheers
aw

Title: Re: What is the effect of ICMR
Post by bharat on Oct 12^th, 2006, 2:18am

If the op-amp is operating other than ICMR the design may end up poor gain and bad CMRR & PSRR.
This is the range of the input when diff pair, active current mirror load and current soure should be in deep saturation. Going the inputs other than this range will result the devices going to liner to cutoff.
Gain:
If the devices are in liner the Gain will go down and the Gain is proportional to gm and in liner region, gm is much less than in the saturation region.
PSRR:
The power supply rejection ratio will deteriorate. Now the diff pair will see a resistive element (devices being in saturation) towards Vcc and Gnd. If it be in saturation, the noise will see huge impedance (of the order of mega ohms) because in saturation region o/p impedance is high. Once it is coming to linear region the devices will be resistive element of few kilo ohms and very much prone of getting injected any noise which is measure of PSRR.
CMRR:
For high CMRR the tail NMOS has to be close to ideal and see a high impedance from that node to GND. If it is not so, the current in current source will more likely be changing and deteriorate the CMRR.

Apart from it BW, voltage offset will also be adveresely affected.

-Bharat

chviswanadh wrote on Oct 11^th, 2006, 4:06am: