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Other CAD Tools >> Physical Verification, Extraction and Analysis >> Maformed device warning fromLVS
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Message started by jaqijak on Oct 13^th, 2006, 5:54am

Title: Maformed device warning fromLVS
Post by jaqijak on Oct 13^th, 2006, 5:54am

Hi!
Does anybody experienced some troubles with multiple transistor design (nfet_mul>1) to design common-centroid current tail? I get a "malformed device" from LVS trying to do this. It seems that LVS identifies two different transistors sharing the same source as a multifinger transistor...

Thanks for your help

Title: Re: Maformed device warning fromLVS
Post by bernd on Oct 13^th, 2006, 8:05am

You usually get a malformed device in Assura LVS when the
extraction step can not proper extract the device terminals.
E.g. the extraction step can not build the device terminals because
they were not drawn correctly or one terminal for the device is missing.

Either your transistor is not drawn correctly or there is a bug
in your command rule files "extract.rul" or in your setup,
run time switches probably.

Quote:

It seems that LVS identifies two different transistors sharing the same source as a multifinger transistor

This is what always happen the extraction step, extracts every single
transistor in your layout, they were then merged later in the process,
if they were parallel, to transistors with multiple gate fingers.

As first step check for mergeParallel in the Assura docs.

Bernd