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Simulators >> Circuit Simulators >> DCop of bias circuit
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Message started by Caspar on Oct 16^th, 2006, 2:34pm

Title: DCop of bias circuit
Post by Caspar on Oct 16^th, 2006, 2:34pm

Hi all,

I've designed a current mirror circuit (attached) for constant gm biasing. Things work as expected when I simulate the circuit in its own cell; I get the correct operating point and my 10 uA current. However, when I introduce this block into another (more complex) schematic, doing the same (DC) analysis produces 'different' results! (all devices turn off). Strangely enough, copying the circuit as a schematic (so not a symbol) doesn't help either. I haven't connected it to any terminals in the big circuit yet, to exclude some freak loading problem.

I know the circuit can operate in multiple states, but I thought that's why the startup device is there. I've also tried putting caps with initial voltage values, no succes. Model libraries, supply voltages etcetera are all the same. Reopening cadence or the ADE doens't help, nor does copying cellviews. I'm actually running two DC analyses on the same circuit, getting different results... :s

Any ideas? Thanks in advance...

Title: Re: DCop of bias circuit
Post by Ken Kundert on Oct 16^th, 2006, 3:11pm

Where is the start-up device? Where ever it is, it must not be doing its job, otherwise all devices off would not be a valid solution.

-Ken

Title: Re: DCop of bias circuit
Post by achim.graupner on Oct 16^th, 2006, 10:33pm

Hi Caspar,

DC find one of the multiple DC operating points. This is one of the dangerous things about simualtion, you never know whether there are multiple operting points.
To force a certain DCop yur have to use nodeset or nodeforce. Initial conditions are evaluated in transient simulation only. The difference between nodeset and nodeforce is well described in Ken's book.

Back to your circuit. If in simulation you dint get the corrent DCop there is a chance the IC after fabrication wont either.

Name you device from left to rigth and from up to down, you get M1-M7 and R1. Now diconnect the gate of M1 and M5. Now you can test the start-up behaviour, a current flow trough R1-M2-M3-M4. Have a llok whether the voltages are meaningful to be used for startup-conditions.

one remark: I am not an expert but I assume that the gate voltage of M4-M7 are quite large. While this is nice for matching it may entail problems regarding saturation of the current sink transistors.

Regards, Achim

Title: Re: DCop of bias circuit
Post by ACWWong on Oct 17^th, 2006, 7:00am

From what I see, the device in the middle of the quad connecting the common pmos gate to the common nmos gate should be a nmos device. (its gate and drain should connect to the common pmos gate and the source at the common nmos gate). Only then will it act as a startup device, ensuring the state of pmos gates at vdd and nmos gates at ground cannot happen.
Often one puts a series R in or two nmos's in series as the startup depending on the supply voltage/potential between the pmos gates and the nmos gates. If you do this i suspect your DCop point problem will disappear. As the circuit is i think the PMOS device in the centre of the quad is redendant and not acting as startup device.

cheers
aw