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Other CAD Tools >> Physical Verification, Extraction and Analysis >> Error while extracting layout
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Message started by kamesh419 on Oct 18^th, 2006, 5:19am

Title: Error while extracting layout
Post by kamesh419 on Oct 18^th, 2006, 5:19am

Dear all,

I am using cadence 5.0.33 and DRC runs fine without any errors (but there are some warnings like "layer purpose fair does not exist in the tech file"). When I try to extract the layout I get the following error.

Quote:

Extraction started at Wed Oct 18 14:57:13 2006

Assuring hierarchy instantiation for:
library: TestBench_kamva881
cell: sramcell_test
view: layout
Rules source is a simple file.
Rules path is /sw/cadence/libraries/HCMOS8D//DK_hcmos8d_4.0/Opus/DK_hcmos8d/divaEXT.rul.
Inclusion limit is set to 1000.
Parsing drcExtractRules of "/sw/cadence/libraries/HCMOS8D//DK_hcmos8d_4.0/Opus/DK_hcmos8d/divaEXT.rul"...
warn: Layer Purpose pair ("contact" "markerR") does not exist in the tech file.
contactR = geomGetPurpose("contact" "markerR")
warn: Layer Purpose pair ("v1" "markerR") does not exist in the tech file.
vi1R = geomGetPurpose("v1" "markerR")
warn: Layer Purpose pair ("v2" "markerR") does not exist in the tech file.
vi2R = geomGetPurpose("v2" "markerR")
warn: Layer Purpose pair ("v3" "markerR") does not exist in the tech file.
vi3R = geomGetPurpose("v3" "markerR")
warn: Layer Purpose pair ("v4" "markerR") does not exist in the tech file.
vi4R = geomGetPurpose("v4" "markerR")
error: Layer cp1nwC is not a device recognition layer.
attachParasitic(nc1 "nc1" cp1nwC)
error: Layer cp1nwC is not a device recognition layer.
attachParasitic(nc2 "nc2" cp1nwC)
info: If short location check is desired later on, check the saveInterconnect statement for correctness:
Interconnect layer mim5, epict, epitie, ndifct, pdifct, dpct, dnct, pstrct, nstrct, subct, subtie not saved.
Interconnect layers merged on save: lilint, lilctp, lilcta.
Interconnect layers merged on save: pstrap, dpter, pdifsi.
Interconnect layers merged on save: nstrap, dnter, ndifsi, sali.
Interconnect layers merged on save: vimim5c, vi5c.

Errors exist in the rules file "/sw/cadence/libraries/HCMOS8D//DK_hcmos8d_4.0/Opus/
DK_hcmos8d/divaEXT.rul".
Verification program terminated."".

Could you please throw some light on where the problem could be. I am using HCMOS8D (0.18u tech) as is evident above.

Thanks and Regards,
Kamesh.

Title: Re: Error while extracting layout
Post by bernd on Oct 18^th, 2006, 8:55am

My assumption;
You are either using a wrong
technology file or you do not have attached the right
technology file to your design library.
Or you have to define a specific switch for extracting you
layout with Diva. You can do this through the user interface.

Do you have any documentations or official support form your
design kit vendor, then you'd better consult them.

Bernd