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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Verilog-A design flow question https://designers-guide.org/forum/YaBB.pl?num=1161181806 Message started by LRC on Oct 18th, 2006, 7:30am |
Title: Verilog-A design flow question Post by LRC on Oct 18th, 2006, 7:30am Hi All, I have written a verilog-A successive approximation register model and simulated it with some transistor-level analog circuits. If I would like to synthesize this SA register model directly to layout, is there a way to do that? Do I need to convert the code to Verilog/VHDL first? Also, does spectre simulate verilog code? Thanks, LRC |
Title: Re: Verilog-A design flow question Post by bernd on Oct 18th, 2006, 9:09am Quote:
What do you mean with synthesis in this context? Synthesis usually means you have described your circuit in a Verilog or VHDL on Register Transfer (RTL) abstraction level and synthesize it to Gate level. Therefore you also need a standard cell library as reference for the synthesis tool. http://www.doulos.com/knowhow/verilog_designers_guide/synthesizing_verilog/ Does this answer this question? Quote:
No, just VerilogA. There are specific Mixed-Signal Simulators which are able to simulate both transistor level and digital as well as mixed signal HDL. Bernd |
Title: Re: Verilog-A design flow question Post by LRC on Oct 18th, 2006, 12:54pm Hi Bernd, Thanks for the help. I see I will need a standard cell library from foundry first. However... When I simulate my mix-signal system using Spectre, my digital component must be written in Verilog-A because spectre doesn't accept Verilog. But later if I were to synthesize the same digital conponent to layout using CAD tool, I have to re-write it in Verilog first. How do I verify the Verilog model I create will still simulate correctly with the rest of the system? The design flow seems broken... Any suggestions? Sorry about asking these elementary questions, I am a beginner in this field. LRC |
Title: Re: Verilog-A design flow question Post by bernd on Oct 19th, 2006, 2:53am Quote:
If you have access you can use a real mixed-signal simualtor like Cadence AMS Designer, Mentors ADVance MS or Synopsys VCS MX. A 'Fast Spice' Simulator like Synopsys Nanosim which support Verilog input can als o do it. Have also a look at this thread: http://www.designers-guide.org/Forum/YaBB.pl?num=1154423549 Bernd |
Title: Re: Verilog-A design flow question Post by jbdavid on Oct 22nd, 2006, 10:19am If you don't have access to those, you might have access to Verilog-XL for the digital side, and you could run the models side by side in SpectreVerilog the Legacy Mixed Signal environment from cadence. |
Title: Re: Verilog-A design flow question Post by LRC on Oct 23rd, 2006, 8:30am Hi, I am simulating my design in AMS environment since the license feature for Verilog-XL is not available to me. I read through the AMS tutorial Cadence provided first and followed the instruction as much as possible. However, when I tried to simulate my design, I kept getting an error saying: ncelab: symbol lookup error: /afs/ece/support/cds/share/image/usr/cds/ldv-5.1/tools/affirma_ams/lib/libsyracuse.so: undefined symbol: __dynamic_cast_2 Error encountered during NC elaboration for configuration SA_AD_verilog:config. In my schematic, there are only analogLib symbols, foundry provided PDK symbols (have AMS siminfo) and a Verilog block. I am not sure what is the "undefined symbol" the error messages refer to. Plus, what is "libsyracuse.so"??? Any suggestions? Thanks for the help. LRC |
Title: Re: Verilog-A design flow question Post by Andrew Beckett on Oct 28th, 2006, 1:53pm Without looking it up, my guess is that your machine does not have the correct OS patches. Try downloading the latest "checkSysConf" program from http://sourcelink.cadence.com and checking whether your patches are up to date for the version of the simulator you're using. libsyracuse is the shared library containing the analog piece of the AMS simulator (if my memory is correct). The missing symbol is due to the libstdc++ you're using being out of date, I think... (that was from a quick google search - I'm not on the Cadence network at the moment so can't check properly). Regards, Andrew. |
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