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https://designers-guide.org/forum/YaBB.pl Modeling >> Behavioral Models >> Verilog-A: the meaning of gnd node? https://designers-guide.org/forum/YaBB.pl?num=1161265487 Message started by Pavel on Oct 19th, 2006, 6:44am |
Title: Verilog-A: the meaning of gnd node? Post by Pavel on Oct 19th, 2006, 6:44am Hello Simulating my schema in Virtuoso-AMS I observed non-desirable spikes on some signals. I've tried to supress them with capacitors: capacitor #(.c(30p)) C1 (OutP); capacitor #(.c(30p)) C2 (OutN); capacitor #(.c(40p)) C3 (DacBuf_InP); capacitor #(.c(40p)) C4 (DacBuf_InN); But if I restart the simulation with modified code, I receive internal error (see attachment). Then I tried following: electrical gnd; ground gnd; capacitor #(.c(30p)) C1 (OutP, gnd); capacitor #(.c(30p)) C2 (OutN, gnd); capacitor #(.c(40p)) C3 (DacBuf_InP, gnd); capacitor #(.c(40p)) C4 (DacBuf_InN, gnd); This time simulation runs, but spike don't disappear. So my question is: Are the instantiations: capacitor #(.c(30p)) C1 (OutP); and capacitor #(.c(30p)) C1 (OutP, gnd); identical? Regards. Pavel |
Title: Re: Verilog-A: the meaning of gnd node? Post by Geoffrey_Coram on Oct 19th, 2006, 10:49am Pavel wrote on Oct 19th, 2006, 6:44am:
I don't think so. I think the first one doesn't specify a connection for the other side of the capacitor, which would mean it is floating. (Since this would have no dc path to ground, the simulator may put GMIN from the second terminal to ground.) |
Title: Re: Verilog-A: the meaning of gnd node? Post by Pavel on Oct 20th, 2006, 12:55am Yes, is true. I checked it with simple example. module GND_NODE_TEST; electrical A, B, gnd; ground gnd; resistor #(.r(10)) R1 (A, gnd); analog begin V(A) <+ 3; V(B) <+ I(A); end endmodule When I measure V(B) it's equal to -0.3V. When I instantiate R1 without gnd: resistor #(.r(10)) R1 (A); compilation passed, but simulation doesn't run and gives initialization error. Regards. |
Title: Re: Verilog-A: the meaning of gnd node? Post by Geoffrey_Coram on Oct 20th, 2006, 5:35am In digital Verilog, leaving a port (terminal) unconnected is well-defined; it's treated as an unknown when an input and as high-impedance when an output. Since Verilog-A is derived from Verilog, it has to follow the same rules. It's a little strange when it iterfaces with Spice, though, because in Spice, terminals must be connected (generally - sometimes, as in BSIMSOI, there are extra terminals for self-heating that are connected conditionally on parameters). |
Title: Re: Verilog-A: the meaning of gnd node? Post by jbdavid on Oct 22nd, 2006, 10:43am In Verilog-A V(A) is the same as V(A,0) where 0 is the analog simulators ground node. If it is NOT behaving this way it is not complying to the LRM. However your simulator may be using a different name for the ground node than you might expect. if your simulators ground node is gnd! and you were using gnd in your models, then those are different nodes... and you'll get "floating" nodes so the problem may have been that ONLY those capacitors were connected to the simulators ground node, so it would be apparently floating. - Make sure you are using the SAME ground node as the analog simulator. Jonathan |
Title: Re: Verilog-A: the meaning of gnd node? Post by Geoffrey_Coram on Oct 23rd, 2006, 5:01am jbdavid wrote on Oct 22nd, 2006, 10:43am:
Jonathan - That's *not* the issue here. I am sure the spice capacitor instantiated per Annex E uses the branch access V(A,B). The question is: if you instantiate something in a Verilog netlist without specifying the connection to a port, what happens to that port? (If you don't specify a parameter override, then the default is used, and the language requires a default in the parameter declaration.) -Geoffrey |
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