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Design >> Mixed-Signal Design >> About capacitors matching
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Message started by ywguo on Oct 19^th, 2006, 10:27pm

Title: About capacitors matching
Post by ywguo on Oct 19^th, 2006, 10:27pm

Hi Guys,

Given the standard deviation Sigma value (say 0.1%) of the matching for two capacitors, which have the same drawn size (say 10um * 10um),
when I want to get ratio of 4 by drawing five (4 vs 1) the same size capacitors (10um *10um),how can I determine the standard deviation Sigma value for this situation? Will the matching be improved or decreased?

It is said that in a pipelined ADC, DNL improves by square of 2 with every extra bit of resolution in the first stages, but why? Because this will improve the matching in the first stage, but how?

Yawei

Title: Re: About capacitors matching
Post by vivkr on Oct 20^th, 2006, 7:53am

Hi Yawei,

Can you mention the reference? I think the author is saying that resolving more bits in the first stage (typically S&H with gain1 ) before passing the signal to the residue amp will => suppression of second stage errors by factor 2^(2n), where n is the number of bits resolved in the first stage.

Mismatch reduction would not give a factor of 2^2n.

Regards
Vivek

Title: Re: About capacitors matching
Post by RobG on Oct 20^th, 2006, 9:59am

ywguo wrote on Oct 19^th, 2006, 10:27pm:

I sure wish someone would write a good tutorial on this stuff -- actually, I wish publishers would realize the need, as they reject the papers ::)...

For the matching of the N:1 case you need to consider each device individually. To do this you divide the matched pair standard deviation by √2. Assuming σ = 0.1% is the standard deviation of the pair of 1x devices, the standard deviation of the 1x device is (0.1%)/√2. Since σ decreases by square-root area, the standard deviation for the Nx device is ((0.1%)/√2N). Finally, the variance for the 1x device paired with the Nx device is
σ^2 = ((0.1%)/√2N)^2 + ((0.1%)/√2)^2, which gives you your answer if N=4.

Note that for N=1, σ = 0.1%, which was the original assumption.

The matching is dominated by the small device. This becomes problematic if you want to make a large ratio.

You might be able to gleen something along these lines from my 2004 CICC Paper... then again, it may be far enough off topic to confuse you more.

rg

Title: Re: About capacitors matching
Post by ACWWong on Oct 21^st, 2006, 1:51pm

RobG wrote on Oct 20^th, 2006, 9:59am:

The matching is dominated by the small device. This becomes problematic if you want to make a large ratio.

Agreed, so best thing is to use series/parallel comninations of bigger unit devices to implement large ratios.
so for 4pF to match 1pF:
you could use 2pF unit (2 parallel for 4pF, 2 series for 1pF, total area is 4*2pF) rather than
4 parallel 1pF and 1*1pF to improve matching..

Title: Re: About capacitors matching
Post by ywguo on Oct 22^nd, 2006, 9:53pm

Hi,

I am sorry that I make a typo in the question.

Quote:

It is said that in a pipelined ADC, DNL improves by square of 2 with every extra bit of resolution in the first stages, but why?

It should be DNL improves by square root of 2 with every extra bit of resolution in the first stages.

The reference is Wenhua Yang, et al., A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist Input, JSSC, Dec. 2001.

Best regards,
Yawei

Title: Re: About capacitors matching
Post by ywguo on Oct 22^nd, 2006, 10:05pm

Hi Robert,

I had read your paper on CICC 2004 before. It is on mismatch of a two-stage opamp, having nothing to do with the cap mismatch.

Quote:

For the matching of the N:1 case you need to consider each device individually. To do this you divide the matched pair standard deviation by √2. Assuming σ = 0.1% is the standard deviation of the pair of 1x devices, the standard deviation of the 1x device is (0.1%)/√2.

As well known, the mismatch is defined as the error between a pair of individual devices. So what is the standard deviation of the 1x device? What's the meaning?

Best regards,
Yawei

Title: Re: About capacitors matching
Post by vivkr on Oct 22^nd, 2006, 11:09pm

Hi Yawei,

sqrt(2) improvement makes sense in terms of matching. I was wondering why you mentioned 2^2 earlier,
and hence asked for the reference. I think Rob has clarified this point quite well by explaining how it works.
I have 1 more points on similar lines to suggest:

The matching is important only when looking at the DAC feedback term in the MDAC output

Vout=2^n.Vin - Gdac.Vref

as the Gdac term is the only one which introduces DNL. If you assume a standard MDAC scheme, then
there are 2^n-1 capacitors which comprise Cs, and 1 capacitor which comprises Cf. Now, Gdac is
realized by the combination of multiple unit caps. Hence, the mismatch terms are being combined
and assuming uncorrelated mismatch between the various caps, the overall error can be expected
to go down in a sqrt() fashion. Does this make sense? It is also worth noting that if you are comparing
2 different MDACs with different number of bits resolved in the stage, then you assume that the unit cap
is the same for both in order to get this result.

Regards
Vivek

ywguo wrote on Oct 22^nd, 2006, 9:53pm:

Hi,

I am sorry that I make a typo in the question.

Quote:

It is said that in a pipelined ADC, DNL improves by square of 2 with every extra bit of resolution in the first stages, but why?

Title: Re: About capacitors matching
Post by David Lee on Oct 22^nd, 2006, 11:41pm

Yawei,

Say we have a pair of identically-layout'ed caps, C1 and C2, with:
σ^2(C1) = ... + σ^2(wafer-to-wafer) + σ^2(chip-to-chip) + σ^2(within-chip) + σ^2(local)
σ^2(C2) = ... + σ^2(wafer-to-wafer) + σ^2(chip-to-chip) + σ^2(within-chip) + σ^2(local)
σ(local) is the local variation of one device, i.e. "the standard deviation of the 1x device".

When we place such a pair right next to each other, we cancel all errors except the last term.
Mismatch is the error between a pair of matched devices, i.e.
σ^2(C1-C2) = 2 σ^2(local)
noting that the σ^2(local) term in σ^2(C1) and σ^2(C2) are statistically independent.

David

Title: Re: About capacitors matching
Post by RobG on Oct 23^rd, 2006, 9:50am

ACWWong wrote on Oct 21^st, 2006, 1:51pm:

RobG wrote on Oct 20^th, 2006, 9:59am:

The matching is dominated by the small device. This becomes problematic if you want to make a large ratio.

Yes, except bottom plate parasitics and the floating node can really mess you up. If you can get around that, it is the best way. It works great for resistors.

Title: Re: About capacitors matching
Post by RobG on Oct 23^rd, 2006, 10:01am

ywguo wrote on Oct 22^nd, 2006, 10:05pm:

Hi Robert,

I had read your paper on CICC 2004 before. It is on mismatch of a two-stage opamp, having nothing to do with the cap mismatch.

You are welcome. I think there is a lot more to that paper than op-amp mismatch.

Quote:

As well known, the mismatch is defined as the error between a pair of individual devices. So what is the standard deviation of the 1x device? What's the meaning?

I know of no paper that explains this well. Kinget's JSSC paper mentions it (you'll have to look it up ~2005). My above referenced paper also mentions it. It boils down to the fact that the two device mismatches are statisitically independent so their mismatches add as the sum of squares. You can take advantage of this fact to look at each device individually, and obtain the σ for more general cases, such as the 4:1 gain.

You need to be careful not to include correlated variations in this calculation. For example, including a global increase in capacitance would give you the wrong answer - remember, only mismatch is important.

rg