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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> coffee maker problem https://designers-guide.org/forum/YaBB.pl?num=1161877602 Message started by lanun_kampung on Oct 26th, 2006, 8:46am |
Title: coffee maker problem Post by lanun_kampung on Oct 26th, 2006, 8:46am hi guys.. i'm a 2nd year electronics n electrical student at UTP.. i need to build a coffee maker using verilog HDL.start from water boiling- mixing -stir -brew...any1 can help.??? :-/ your help is appreciated :) |
Title: Re: coffee maker problem Post by bernd on Oct 26th, 2006, 9:19am Sounds like a Finite State Machine http://en.wikipedia.org/wiki/Finite_state_machine The most common student exercise for that is the traffic light, maybe this may help you as a starting point. http://www.cs.technion.ac.il/~cs236346/tlc.v (Just found through Google, not tested) Bernd |
Title: Re: coffee maker problem Post by lanun_kampung on Nov 9th, 2006, 8:37am tq... this is my program. i'm using quartusII //timer module clock_div (Q0,CLK,coffeetype); input CLK; input coffeetype; output Q0; reg CLKdiv; reg [23:0] i; initial begin i=0; CLKdiv=1'b0; end always @ (negedge CLK) begin if(coffeetype) begin if (i<24'b111111111111111111111111) i=i+1; else begin i=0; CLKdiv=~CLKdiv; end end else begin if (i<24'b110000000001000111101100) i=i+1; else begin i=0; CLKdiv=~CLKdiv; end end end assign Q0=CLKdiv; endmodule //water sensor module water_sensor (waterstatus,warninglight,CLK, waterlevel); input waterlevel,CLK; output waterstatus,warninglight; reg waterstatus,warninglight; always@(posedge CLK) if (waterlevel==1) waterstatus =1'b1; //boilerNotEmpty else waterstatus =1'b0;//boilerEmpty always@(posedge CLK) if (waterlevel==1) warninglight = 1'b0; else warninglight = 1'b1; endmodule //warmerplate sensor and valve pressure module plate_sensorAndvalve_pressure (openclose,platestatus,CLK, pot); input pot, CLK; output openclose,platestatus; reg openclose,platestatus; always@(posedge CLK) if (pot==0) platestatus = 1'b0; //turns off plate warmer else platestatus = 1'b1; //restart plate warmer always@(posedge CLK) if (pot==0) openclose = 1'b1; //open valve to stop water flow else openclose = 1'b0; //close valve to start water flow endmodule //mixture sensor module mix_sensor (mixstatus,warninglight1,mixsense); input mixsense; output mixstatus,warninglight1; reg mixstatus,warninglight1; always @ (mixsense) case(mixsense) 1'b0 : mixstatus = 1'b0; // indicate that there are no mixture in the container 1'b1 : mixstatus = 1'b1; // indicate that there are mixture in the container endcase always @ (mixsense) case(mixsense) 1'b0 : warninglight1 = 1'b1; // turn on mixture-warning light for error 1'b1 : warninglight1 = 1'b0; // mixture-warning light is off if there are mixture in container endcase endmodule //main coffee maker program module coffee_maker(dispenserfilter,Q0,boiler,warmerplate,timer,mixcontainer,mixstatus,warninglight1,waterstatus,platestatus,valve,Button,Setclock,CLK,pot,waterlevel,warninglight,mixsense,coffeetype); input Button,Setclock,CLK,pot,waterlevel,mixsense,coffeetype; output dispenserfilter,Q0,boiler,warmerplate,mixcontainer,waterstatus,platestatus,valve,warninglight,mixstatus,warninglight1; output [4:0]timer; wire START; reg [4:0] timer; reg mixdispenser,boiltimer,timingprocess; assign START = (Button||Setclock)&& timingprocess; //instantiate water sensor water_sensor WS(waterstatus,warninglight,CLK, waterlevel); //instantiate plate sensor and valve pressure plate_sensorAndvalve_pressure PSVP(valve,platestatus,CLK, pot); //instantiate mixture sensor mix_sensor MS (mixstatus,warninglight1,mixsense); assign boiler = START && waterstatus && mixstatus && boiltimer ; // to make boiler heater turn on or off assign #(100) warmerplate = START && platestatus && mixstatus ; // to make plate heater turn on or off assign #(200) mixcontainer = boiler && warmerplate ; // to make mixute container open or close assign dispenserfilter = START && mixdispenser; //instantiate timer clock_div CD(Q0,CLK, coffeetype); always@(posedge Q0) begin timer=timer+4'b0001; end always @(timer) begin case(timer) 4'b0101: begin mixdispenser=1'b1; end 4'b0110: begin mixdispenser=1'b1; end 4'b0111: begin mixdispenser=1'b1; end default: begin mixdispenser=1'b0;end endcase end always @(timer) begin case(timer) 4'b0000: begin boiltimer=1'b1; end 4'b0001: begin boiltimer=1'b1; end 4'b0010: begin boiltimer=1'b1; end 4'b0011: begin boiltimer=1'b1; end 4'b0100: begin boiltimer=1'b1; end 4'b0101: begin boiltimer=1'b1; end 4'b0110: begin boiltimer=1'b1; end 4'b0111: begin boiltimer=1'b1; end 4'b1000: begin boiltimer=1'b1; end 4'b1001: begin boiltimer=1'b1; end 4'b1010: begin boiltimer=1'b1; end 4'b1011: begin boiltimer=1'b1; end default: begin boiltimer=1'b0;end endcase end always @(timer) begin case(timer) 4'b0000: begin timingprocess=1'b1; end 4'b0001: begin timingprocess=1'b1; end 4'b0010: begin timingprocess=1'b1; end 4'b0011: begin timingprocess=1'b1; end 4'b0100: begin timingprocess=1'b1; end 4'b0101: begin timingprocess=1'b1; end 4'b0110: begin timingprocess=1'b1; end 4'b0111: begin timingprocess=1'b1; end 4'b1000: begin timingprocess=1'b1; end 4'b1001: begin timingprocess=1'b1; end 4'b1010: begin timingprocess=1'b1; end 4'b1011: begin timingprocess=1'b1; end default: begin timingprocess=1'b0;end endcase end endmodule |
Title: Re: coffee maker problem Post by Geoffrey_Coram on Nov 10th, 2006, 5:07am lanun_kampung wrote on Nov 9th, 2006, 8:37am:
Why is this done as two always blocks, rather than Code:
I also might suggest a `define to keep track of the meanings, ie `define BOILER_EMPTY 1'b0 `define BOILER_FULL 1'b1 -Geoffrey |
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