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https://designers-guide.org/forum/YaBB.pl Design >> RF Design >> cmos resistor in rf design https://designers-guide.org/forum/YaBB.pl?num=1161900098 Message started by chenyan on Oct 26th, 2006, 3:01pm |
Title: cmos resistor in rf design Post by chenyan on Oct 26th, 2006, 3:01pm when use resistors in rf design (GHz range), in order to choose right width, flick noise, matching, current density and parasitics should be considered. But did I miss something? Is there anything else affect the choice of width? |
Title: Re: cmos resistor in rf design Post by ACWWong on Oct 27th, 2006, 2:03am things as well as those you mention include absolute tolerance, temp coefficent, voltage coefficient (if usingdiffused resistor) and match to any bias/bandgap resistor type... also remember the contacts have different paramters to the resistor body. For RF you should use poly (or even better metal (deposited nichrome or tantalum nitride) resistor), in which case you don't get flicker noise or voltage coefficient. Critical is the choice of width/length/multplier (parallel/series combination) to get the best matching to parasitic/area balance. Check out Alan Hastings' book "art of analog layout". |
Title: Re: cmos resistor in rf design Post by chenyan on Oct 30th, 2006, 6:52am Thank you, ACWong! The same question for cmos capacitors, how to get a optimized w/l ratio? certainly a square helps matching and reduce parasitics, but what else? Q factor? I simulated with mimcap and vppcap, it seems both have the best Q when they are squares and what if it is a "NFET in NWELL" cap? then I really have no clue, channel resistance? maybe, but what is the optimum? |
Title: Re: cmos resistor in rf design Post by chenyan on Oct 30th, 2006, 6:54am In some books, authors also insisted w/l ratio of 2 for mimcap is the best for Q, and I really dont see any reason why. |
Title: Re: cmos resistor in rf design Post by ACWWong on Oct 30th, 2006, 10:54am rfmems wrote on Oct 30th, 2006, 6:52am:
square is best for MIM NFET in nwell... for RF the Q is usually pretty crummy, but yes you need to optimise channel resistance and poly resistance, so it comes down to the sheet resistance of your poly and nwell... probably you'll make it a bit wider as nwell is probably more resistive (although some of these structures use N+ especially in BiCMOS where the N+ is a BJT collector.) Anyway for both MIM and poly-insulator-semiconductor (i like to call them PIS) caps you should concern your self with which plate has the parasitic and connect your caps with this in mind. In the case of MIM, its easy to ensure your top plate is at most RF sensitive node. In the case of PIS, its also easy to see the parastic nwell to psub diode is on the Nwell plate... but also remember the higher the voltage on the Nwell plate, the more reverse biased the parasitic diode is, so the better for higher frequencies... of course you will be need to make sure the voltage charactersitics of the main cap is ok! |
Title: Re: cmos resistor in rf design Post by ACWWong on Oct 30th, 2006, 10:56am rfmems wrote on Oct 30th, 2006, 6:54am:
which book is this ? |
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