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Design >> Analog Design >> How can i implement a 'time-variable capacitor'
https://designers-guide.org/forum/YaBB.pl?num=1162169982

Message started by Davidy on Oct 29^th, 2006, 4:59pm

Title: How can i implement a 'time-variable capacitor'
Post by Davidy on Oct 29^th, 2006, 4:59pm

I am beginning the research on weak capacitive signal pickup circuits design. I my research work I need generate a time-variable capacitor (Cs in the figure below) in Cadence and simulated it using Spectre.Cs is changing its capacitive value in a frequncy of 1kHz.

I have tried making a Cs using VerilogA language. But this can only generate varible current and is not fit my usage.
Recently I find a paper about 'variable capacitor '. But it is described in Pspice. I really want to kown if it can also used in Cacence Spcetre and how to do it.

Can you give a suggestion about it?

Title: Re: How can i implement a 'time-variable capacitor
Post by Davidy on Oct 29^th, 2006, 5:03pm

And this is the paper about "variable capacitor" which is descibe in Pspice.

Who can give me some advice how can I draw a similiar 'cap' in Cadence with the compenents in the library "analogLib" and simulate with spectre?

Thanks a lot!

Title: Re: How can i implement a 'time-variable capacitor
Post by Ken Kundert on Oct 29^th, 2006, 11:34pm

Try reading http://www.designers-guide.org/Modeling/varactors.pdf.

-Ken

Title: Re: How can i implement a 'time-variable capacitor
Post by Davidy on Oct 30^th, 2006, 3:22am

Thank you!
I will read that paper right now.