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Measurements >> Phase Noise and Jitter Measurements >> Divider or buffer phase noise simulation question
https://designers-guide.org/forum/YaBB.pl?num=1162437178

Message started by aren on Nov 1^st, 2006, 7:12pm

Title: Divider or buffer phase noise simulation question
Post by aren on Nov 1^st, 2006, 7:12pm

I read Ken's PLL Phase noise and jitter simulation paper. It recommend that for the ripple counter style divider, we need simulate each divider seperately and then combine them together. My question is why? If I treat the whole divider as one circuit and do a PSS/PNOISE simulation. Why is this way not accurate? The same thing for the clock buffers. If I have 5 stages of clock buffers, should I simulated five of them and then combine? Thanks.

Title: Re: Divider or buffer phase noise simulation quest
Post by Ken Kundert on Nov 1^st, 2006, 10:26pm

You can do that, it just gets expensive. This is especially true for dividers, because the frequency keeps dropping as you add stages. Two stages will be 4 times more expensive than simulating one stage, because it two stages are twice as large, and the simulation period is twice as long.

-Ken

Title: Re: Divider or buffer phase noise simulation quest
Post by aren on Nov 2^nd, 2006, 7:33am

Ken Kundert wrote on Nov 1^st, 2006, 10:26pm:

Thank you very much, Ken. I understood the simulation time issues now. Besides the simulation time, is there any accuracy issue if I simulate the circuit as a whole? Thanks.

Title: Re: Divider or buffer phase noise simulation quest
Post by abcd on Nov 2^nd, 2006, 8:24am

Hello, guys,

I just ran a small test with 5 stages of identical CML buffers connected in series. The small signal gain of each CML buffer is about 2.7. The slew rate and signal swing for the first stage input has been set close to those of the following stage input. Time domain Pnoise simulation was used to check noise voltage PSD at stage 2, 3, and 4 outputs since they have exact same input and output characteristics. In the Pnoise simulation, only one point was simulated and the time of that point had been measured from PSS simulation for each stage Pnoise simulation. Three Pnoise simulations had been run. The following is the simulation results measured at 1MHz offset freq (the carrier freq is 75MHz),

stage 2 output: -140.12dB
stage 3 output: -139.48dB
stage 4 output: -139.43dB

The above numbers look almost the same. I have also checked the "Noise Summary" for noise contribution in each of the above simulation. The noise contribution is dominated by the immediate upstream stage. For example, for stage 3 output, noise contribution is dominated by devices in stage 3. Devices in stage 2 and stage 1 have little contribution and devices in stage 4 and stage 5 have no noise contribution.

Now, I'm confused. In the real world, I may have to simulate the total pnoise of three buffers. If I simulate them all together in one simulation as Ken mentioned earlier, I would setup simulation just like what I have done here with stage 1 as the driver and stage 5 as the loading. Then, the total noise for the three buffers would be -139.43dB at 1MHz offset. I expect devices in stage 2 and stage 3 should have quite a bit noise contribution since the stage gasin is > 1, but I didn't see this, the noise is dominated by devices in stage 4 only.

If I characterize each stage at a time just like what we did in the ripple counter, I could setup simulation just like what I did in the previous simulation as well since the noise contribution from other stages are small, and the simulation result is the noise (mostly) from the current stage. Now, the total noise of these three buffers is three times that of each stage or three times of stage 4.

In other words, if I process the same thing in two diffreent ways, the result from one is about three times that of the other one.

I don't know if I have done something wrong here. Please help.

Title: Re: Divider or buffer phase noise simulation quest
Post by Ken Kundert on Nov 2^nd, 2006, 8:33pm

Yes, you must have done something wrong. Each stage should contribute the same amount of jitter.

-Ken

Title: Re: Divider or buffer phase noise simulation quest
Post by rf-design on Nov 2^nd, 2006, 11:50pm

I did have the same issue 4 years ago. The situation does not change up to now, from the tool side or from my understanding.

http://www.designers-guide.org/Forum/YaBB.pl?num=1036411197

Title: Re: Divider or buffer phase noise simulation quest
Post by Lance on Apr 18^th, 2007, 6:29am

In my case I want to measure the phase noise in a ripple cml divider made up of 2/3 sections. To get the overall current down each stage has half the frequency of its previous so my slew rates will get worse each stage and hence the jitters will get progressively worse and will not be the same for each stage. I believe this means I can not measure the phase noise as a whole but measure each 2/3 stage separately and add all the jitters then multiply by the lowest stage frequency to get the phase noise. Is this correct anyone?