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Design Languages >> Verilog-AMS >> [q] verilog-a in hspice
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Message started by kidhyun on Nov 7^th, 2006, 12:35pm

Title: [q] verilog-a in hspice
Post by kidhyun on Nov 7^th, 2006, 12:35pm

Hi,

Pleae let me know how to pass parameters when I instantiate verilog-a module in hspice.
For example, there is a resistor module in verilog-a.
Then in hspice I have to do
.hdl 'resistor.va'
x1 a b resistor // when resistor is the module name

The how can I pass a parameter value (resistor value) here?
Do I have to make seperate verilog-a module for each resistor with different resistance?

Thank You

Title: Re: [q] verilog-a in hspice
Post by Geoffrey_Coram on Nov 8^th, 2006, 10:27am

Did you try

x1 a b resistor r=10k

where "r" is the parameter declared in the module?

I believe the HSpice implementation also allows model cards, eg

x1 a b myres
.model myres resistor r=10k