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Message started by aval on Nov 8^th, 2006, 1:45am

Title: Series transistors
Post by aval on Nov 8^th, 2006, 1:45am

Hi,

I need to increase the lenght of a transistor in the design to about 6 times its current size. The current lenght is at the max allowed by the process. One way to do this is to put 6 transitors in series of the same W/L in series. This should result in W/(L*6).

As far as I know this is a valid implementation. The simulator however interprets this differently (of the 6 series transistors 5 of them will be in triode). Are any results different because of this? Do I have to look out for anything in such an implementation?

These transistors are being used for current mirrors and the two NCH loads of a diff-amp.

thanks in advance
A.

Title: Re: Series transistors
Post by vivkr on Nov 9^th, 2006, 2:06am

Hi,

I think it should normally not be a problem. However, you should make sure of 2 things:

1. The model of the transistor used in schematic (6*L) may be different from the one you
actually have in physical implementation.

2. Due to the above, you may have poorer output impedance. Just run a simulation to check
how the block behaves with the correct transistor arrangement.

Regards
Vivek

Title: Re: Series transistors
Post by aval on Nov 9^th, 2006, 8:18am

Hi Vivek,

Thanks for responding.

>>1. The model of the transistor used in schematic (6*L) may be different from the one you
>>actually have in physical implementation.

The physical implementation matches schematic drawing. The schematic also has 6 transistors in series (similar to layout). Is that what you are referring to here? All simulations are with series transistors as well.

The reason I ask this question is that I saw some odd behavior in simulations. I was using these transistors as loads for the first stage of a miller compensated two stage diff amp. This diff amp is a part of a bandgap reference. At a few corners, for transient sims, the amp rails to an impossible state (+ve input > -ve input, output railed to ground).

DC operating point and PM/GM/loop gain simulate fine. Nothing is borderline. This odd state shows up only in transient sims.

This happens only if the start-up circuit is connected (during start-up, the output is forced to ground). An external enable pulse is used to control the start-up circuit. The start-up circuit is off when the opamp is in the railed condition.

Reducing the miller cap drastically doesnt force the opamp to oscillate either. Spice and spectre give me the same results.

Any ideas??

cheers,

Andy.

Title: Re: Series transistors
Post by ACWWong on Nov 9^th, 2006, 12:54pm

Hi aval,
try posting a diagram.. it might help you get a better replies... but your startup circuit sounds iffy.
btw i am not quite clear how this/why this 6*L thing works... can;t you just use cascode load to increase output impedance ?
cheers
aw

Title: Re: Series transistors
Post by vivkr on Nov 9^th, 2006, 11:25pm

Hi Andy,

Could you please post the schematic? I think your problem may lie outside the amp itself.

ACWWong's suggestion of using a cascode is wise if you have the headroom for it, although I think
your amp is still fine. Possibly, there is some issue with your startup network.

Regards
Vivek

Title: Re: Series transistors
Post by vivkr on Nov 9^th, 2006, 11:30pm

ACWWong wrote on Nov 9^th, 2006, 12:54pm:

Hi,

I agree that a cascode may also be a good idea when the headroom is available. However, to answer your question, placing several
devices in series effectively increases the L, just as placing many in parallel would increase the W. You can think of it more easily
if you consider that even a single MOS transistor may be visualized as a distributed device, with several smaller devices combining in
series (split the channel into equal parts), and tied to the same Gate and Bulk. Although the channel pinches off towards
the drain end, there is still a channel present below the pinchoff point.

Considering the MOS device once more as a series of smaller MOS devices, it is easy to see that only some of the devices at the end
have their channels pinched-off, while the rest do not. Hence, the simulation shows all but one devices as operating in the linear region.

Regards
Vivek

Title: Re: Series transistors
Post by SRF Tech on Nov 10^th, 2006, 6:50am

The practice of using series resistors to create the effect of larger channel length is common and approrpriate.

If you actually integrate Id over the the channel lengths: ∫Id dy1 + ∫Id dy2 (where dy1 is the channel of one device and dy2 is another device, in series) they are actually equivalent to a single device of the summed up channel lengths.

i.e. ∫Id dy1 + ∫Id dy2 = ∫Id dy_total

What you discover is that it is impossible to have more than one device, in a series string, that is in saturation, as it turns out the superior device in the series will always be the only device in saturations and the rest should be in linear ( I would bet that that is what your simulator is stating). If anyone wants the math behind it I have it written down from an analysis I did several years ago.

So yes, it is a valid implementation and yes your simulator is simulating it correctly. If you are still unsure, a perfectly valid way to test the theory is to simulate/plot the standard MOS I-V curves with Id versus Vds with Vgs swept, using your serie devices as a single transistor. You should get reasonable plots.

I should also mention, that the macro device, if not bias correctly will show all devices in linear just as if a single device of that channel length (6*L) was in linear. So my comments are directed to the situation that the macro device is biased in saturation.

Title: Re: Series transistors
Post by aval on Nov 10^th, 2006, 7:53am

Thanks all for your replies. The opamp circuit is attached. Its the transistor series that is marked up as M2 and M3 that is giving me grief. It is currently shown as 4 in series because thats what works in sims.

The reason I have so many in series is to increase the overdrive. This is a low power implementation (15nA Id). The original implementation had just one transistor (the weakest possible for the models) which had an overdrive of 1mV ( :-/ ) at some corners.

To increase the overdrive, I weakened the transistors. Increasing current was not an option. The maximum I could increase the channel length by for the current mirror loads (M2 & M3) was 4*L. Anything more series transistors, the opamp went into the odd railed state at some corners. Nothing else seems to affect this entering into the odd state.

To answer the other question about doing some comparative sims : I did do a couple. I did some sims with 3 series transistors (3u = L each) and one transistor with L = 9u. The Ws were the same.

One set of sims was to vary id and measure vgs. The delta between the vgs's was at max 5%. The other simulation I did was keep vgs constant and vary vds. The delta between the series transistors and single transistor was about 25%.

I will attach the BGR picture separately. The startup circuit is just a NCH that pulls the pbias_u (output of the opamp) low during POR and is shown in bgr.png.

thanks,
Andy

Title: Re: Series transistors
Post by aval on Nov 10^th, 2006, 7:57am

BGR picture attached. The circuit diagrams are turning out to be big. Do you have any suggestions to make them smaller? The opamp shown in bgr.png was attached with the earlier post.

In the bgrOpamp figure, the grounds seem disconnected in the circuit. They are not.

cheers,
Andy

Title: Re: Series transistors
Post by loose-electron on Nov 13^th, 2006, 8:59am

The bulk connection of the M2 side of your current mirror (under the differential pair) are all tied together, but not tied to ground.

Tie the body to ground and see if that changes things.

Title: Re: Series transistors
Post by aval on Nov 13^th, 2006, 10:01am

Thanks for the response.

The bulk connections are all implicitly (by naming the net) or explicitly tied to ground.

Sorry for the misleading schematic. It comes from multiple edits to opt in and opt out those series transistors (and not having a cleaned up snapshot of the schematic at home to post).

Oh yes the input transistors of the first stage is in subthreshold and so is M6. All current mirrors are in saturation.

I find that I see this problem even if I add a resistor of the order of 2M to these series transistors (4 series transistors + 2M resistor in series). The 2M is because thats what the gds of each of those triode transistors simulate to be. Just another data point for me.

thanks& regards,
andy

Title: Re: Series transistors
Post by loose-electron on Nov 13^th, 2006, 2:41pm

Andy:

The currents that you are at are such that parasitics are going to affect the transient and statrtup of the circuit in a big way. Also, ask the question if the models are valid at the nA currents that you are using?

What is the foundry process and model set from? A lot of foundries have invalid models down at the currents that you are using.

If your models are good (important that you question this strongly!) you may want to leave a single current mirror structure at the bottom (just 2 transistors, or 4 if you have the headroom for a cascode current mirror instead) and instead drop the PMOS current source way down instead.

Question the models, and then ask what is available to reduce the current. Resistors probably are not going to get it done due to area required.

Some micropower processes (I am thinking Medtronics and other that do IC's for things like pacemakers) have good micropower models and also make availalble a high-R poly layer (like 300K ohm per square) but that is not the case here probably.

Title: Re: Series transistors
Post by imd1 on Nov 14^th, 2006, 4:15am

I am not sure, and I suppose you have checked this circuit throughout, but it sounds to me like the systematic offset is getting
out of hand at some corners, and this is driving the output to the rails.

I assume that you have sized the current sources so that you have equal current densities in the input stage mirror and the output stage device. If this is the case, then your output device is *not* matched to the composite series transistor device in the input stage, and the simulator (depending on the model you use...) may pick different model bins for each one of them. Both the composite device and the output device behave the same (region of operation, etc) in some situations, but at some corners the predicted current for each is far enough apart that the output rails. Since it goes to Vdd one knows that the ouput device is drawing less current than it should. Use a composite series device in the ouput stage and resimulate to check for this.

As already mentioned you will be boldly pushing the foundry model where it has never gone before, so your design "as is" may actually work fine (long devices, not too narrow) ,... or not. Using the same unit device in the input and output at least gives you the comfort of meeting qualification tests, and if totally wrong then you'll have some interesting discussions later with the test engineer once the chip is back and on the bench.

Been there, btw, w/ something very similar.

Title: Re: Series transistors
Post by loose-electron on Nov 18^th, 2006, 11:57am

"interesting discussions"

hm... lets not forget, that run into the foundry will cost you between $50K and $1.4 million...

Suggest having a dialog with the foundry model group on the validity of the models, both size and current range.

THis is a must have. Know the limits of you models, or be willing to burn the $$$ and time.

Jerry

Title: Re: Series transistors
Post by Croaker on Nov 21^st, 2006, 8:58pm

Well, if you put two MOSFETs in series (gates connected together), the top FET needs at least a Vth drop to be on, so the bottom FET will have a drain voltage that is at least one Vth below its gate voltage; the bottom FET is not in saturation.

It's not too tricky to show this config behaves like a single MOSFET with W/(2*L). Just set I1=I2 for the cases where the top is saturated or linear.

I believe it's always better to use the same L, firstly because the nominal Vth is the same, and also because each L sees the same diffusion variation (i.e. Leff = L - Ldiff - Xd). Right... 6*(L-0.2) gives a desired ratio, vs. 6L-0.2 (i.e. not 6 times the length of a single FET).

For those series transistors, the body effect of course is going to come into play and reduce current drive.

Title: Re: Series transistors
Post by vivkr on Nov 23^rd, 2006, 12:43am

Croaker wrote on Nov 21^st, 2006, 8:58pm:

For those series transistors, the body effect of course is going to come into play and reduce current drive.

Hi Croaker,

This argument seems thin. There should be no additional problem due to body effect in a series cascade of transistors as in a single MOS
device. After all, each segment of the channel (going from source to drain) has the same voltage distribution in either case, and so the body
effect is the same. It is misleading to treat devices in series as separate transistors as this leads to confusing deductions.

Regards
Vivek

Title: Re: Series transistors
Post by Croaker on Nov 23^rd, 2006, 7:29am

Hmm, two series transistors look just like a 2*L single transistor: i=k*w/(2*l)*(Vgs-Vth)^2. However, the derivation to show this assumes the Vth in each transistor is equal.

So what value of Vth should be used for the equivalent transistor? The top transistor Vth is larger than the bottom one due to body-effect.

Assuming Vth stays constant with L, the long transistor should be driving more current than the series combination. It gets the full Vgs and Vth does not have body-effect. In the series chain, the Vgs for each additional transistor is a little less than the one before it, and each source is higher than the lower sources; less Vgs and higher Vth.

My point was I think there is a difference between one long one and a series chain. I hadn't thought about it too deeply before seeing this discussion.

Personally I'd use the series chain in order to keep the same L throughout the design (better for ratioing and Vth may vary significantly with L)

---

Here's a sim I did with 5 series transistors vs. one long one (m5 is the top of the series chain):

element 0:m1 0:m2 0:m3 0:m4 0:m5 0:meq
model 0:nfet 0:nfet 0:nfet 0:nfet 0:nfet 0:nfet
region Linear Linear Linear Linear Saturati Saturati
id 3.8642u 3.8642u 3.8642u 3.8642u 3.8642u 4.0681u
ibs 0. -241.9926a -516.9747a -843.8618a -1.2720f 0.
ibd -241.9926a -516.9747a -843.8618a -1.2720f -3.0000f -3.0000f
vgs 1.0849 1.0607 1.0332 1.0005 957.6938m 1.0849
vds 24.1993m 27.4982m 32.6887m 42.8133m 172.8005m 300.0000m
vbs 0. -24.1993m -51.6975m -84.3862m -127.1995m 0.
vth 799.7621m 806.9361m 814.9445m 824.2769m 836.2111m 801.5393m
vdsat 246.6516m 220.0844m 189.8273m 153.7734m 106.4267m 245.7596m

Title: Re: Series transistors
Post by vivkr on Nov 23^rd, 2006, 8:21am

Hi Croaker,

Let's put your argument to a simple test. I take one single transistor of L=10um. Now, travelling along the channel with the
device in saturation, I see a varying channel potential with respect to gate as I travel from source (x=0) to drain (x=L).

For the moment, let's ignore all the various effects such as difference between drawn length and
actual length etc. that make a single transistor different from a series of several devices. Let us assume that
this splitting of the transistors is done only for the purpose of analysis.

I can split the channel at any point to create 2 sub-MOSFETs from one single device. I could for example split
the channel at x=5um to get 2 transistors with L=5um each. Now, the source voltage for the top transistor is say Vs1.

Again, I do a different kind of split, splitting the MOS at x=1um to get 1 MOS with L=1um, and another with L=9um.
The top transistor (9um) has source potential Vs2.

Vs2 < Vs1. So, Vth is larger for the top device when I split it into 5um-5um instead of 1um-9um, but it is the same 10um device.
As you can see, there are infinite possibilities for splitting L into 2 or more sub-devices in series, but all of them are the same device,
because a real MOS has a channel which has a finite length. Would there be a different amount of body effect simply because I choose to
analyze the same MOS in different ways?

Real scenarios will be slightly different because the drawn length is not the same as the actual channel length due to various errors
in processing. But, the difference is only because of this, and not because there is any extra body effect.

Perhaps, someone can find a flaw in my reasoning.

Regards
Vivek

Title: Re: Series transistors
Post by Croaker on Nov 23^rd, 2006, 9:06am

That intuitively makes sense to me. I mean, physically, it seems right, since two in series have almost the same structure as a double-length one (except there is an implant in the middle of the series chain).

Well, I just worked out the equivalence and if you include body effect you'll get the result that two MOS in series kind of looks like a single 2*L MOSFET, but with an error term of:

k*W/2*(2*L)*(Vg - Vth)^2 + k*W/2*(2*L)*( -2*dV*(Vg - Vth) + Vx*dV + dV^2 )
^ looks like 2*L device ^ body effect error term

Vth2 = Vth1 + dV, and Vx is the drain voltage of M1. M2 is the top device, M1 is the bottom device.

I think I established through my simulation and my equation above that there is a difference, however slight, between the two structures. I think your statement about it not mattering how you split the L is true for a continuous channel, but perhaps not when there are implants between the top drain and bottom source.

With a long device, there is no body-effect, but if you start putting implants in the channel, each new device will have some body effect.

Title: Re: Series transistors
Post by imd1 on Nov 24^th, 2006, 3:59am

Hi all,

regarding the posts about equivalence of n series devices to a single one of n*L length, I'd say there's no difference, if
one ignores geometric effects (undercuts, etc). The implant is of the same type as the channel, so it forms a continuous
conducting path from one end to the other of the composite device. One long device is then equal (minus the geometric effects, etc) to several short ones in series, I agree with Vivek.

The implant will also introduce additional capacitance, and, leakage current, which *may* be the problem of the original post,
since it's biased at a few nano-amps, if I understood correctly. I don't know what is his/her testbench, or on what corner the problem appears (high temperature, high leakage ?).

My point in my earlier post was that , since the composite device and the output device aren't matched, and operate in different
regions (one in quadratic, the other in subthreshold), the simulator/model problems are possibly being magnified, and on some
corners it leads to large errors in the predicted current. It depends also on the testbench, is it a closed-loop transient analysis?
MC, including perhaps geometry variations ?

Title: Re: Series transistors
Post by Croaker on Nov 24^th, 2006, 4:32am

Yeah, I think they should be the same, but I'm having trouble reconciling this with my analysis. It doesn't take into account anything besides the fact that the top transistor will have a different Vth due to body-effect.

Title: Re: Series transistors
Post by RobG on Nov 30^th, 2006, 12:59pm

I'm sorry I don't have a reference... but I'm pretty sure the body effect term is cancelled by something else so that two devices in series is the same as one with twice the L (possibly neglecting L's effect on Vt). I had this discussion with Dan Foty of Gilgamesh... he may have something in his book on modeleing devices. In other words, Vivek is correct.

At any rate, mosfets in series are (supposedly) a good way to accurately scale down a current by an integer, but here is the catch: BSIM simulations get it wrong. The reason, according to Foty, is that BSIM uses a source-based model. I don't understand what this means, but the take home point is that you need to be wary of the simulation results... there is something fundamentally wrong with the model when used for series devices.

One other thing, if the devices are not the same size you can get unexpected effects. For example, if the top MOSFET is in subthreshold, and the bottom transsitors are not, the top device will act as a cascode device, with the bottom device being fully saturated. This is called "self cascode" and is a common way to get a cascode without headroom loss if speed isn't an issue.

Personally, I've always had scary results when simulating series mosfets... it seems like they are always doing something funny unless I have long channels and have lots of overdrive (say 150mV or more). I personally try not to put them where it is important.

rg

Title: Re: Series transistors
Post by Croaker on Nov 30^th, 2006, 1:51pm

RobG wrote on Nov 30^th, 2006, 12:59pm:

Dan would be the guy who knows! If you can remember, please post.

Perhaps a source-based model means the device is not treated as truly symmetrical. No clue.

Title: Re: Series transistors
Post by RobG on Nov 30^th, 2006, 2:04pm

Croaker... this is one of those questions that has always nagged me... I actually made a test chip to see how all this played out. It was a mirror with two outputs. The first output was a 1x device. The second output was two series devices in parallel (i.e. four devices). In theory, both should have the same current if the series device gives 1/2 the 1x current. The chip had an array of 256 of these pairs so I could eliminate random effects. I think I also had a 6b dac that used the series devices (like a M-2M dac).

I never found the time to fire up that test chip to measure those things. Now that I'm back in school I may go find that chip and see if I can't get a paper out of it...

Title: Re: Series transistors
Post by Croaker on Nov 30^th, 2006, 8:38pm

Hey wait, if the BSIM model is flawed for series devices, that strikes me as very bad. There are series devices all over the place! :o

Are there specific cases where one has to be wary?

Title: Re: Series transistors
Post by RobG on Nov 30^th, 2006, 9:34pm

Here is a simulation you can run. All transistors are W=20um amd L=10um (to keep things simple). The currents I1 and I2 should be equal, as should I3 and I4. I've plotted the ratio I2/I1 and I4/I3 versus the bias current (the current source on the far left). As you can see from the plot in the next post, there is a fair amount of error.

If we keep the gate/drain voltage constant, this error seems to be less than 10% (this is I2/I1). However, if the drains of the transistors are fixed while the gate votlage increases there is substantial error... the ratio is 0.6 at low currents when it should be unity. For what it is worth, the Vgs-Vt is 1.9v at 1mA for this process.

Keep in mind that I've never been able to verify that this is indeed a model error, and not something that happens in real life. I got the impression from Foty that in silicon I2 will match I1, and I3 will match I4. His take was that the EKV model handles this type of circuit correctly.

Title: Re: Series transistors
Post by RobG on Nov 30^th, 2006, 9:45pm

Here is the plot of the ratios (which should be unity) versus current for the circuit in the above post.

Title: Re: Series transistors
Post by vivkr on Dec 1^st, 2006, 1:17am

Croaker wrote on Nov 23^rd, 2006, 9:06am:

Hi Croaker,

Quite many replies on this topic I see. I just have a quick question. How did you do the above derivation? I think you would need to make certain assumptions about the region of operation of each transistor which may/may not hold. Anyway, regarding the BSIM3 models being source-based, your understanding of this is correct (model source-oriented instead of bulk-oriented in BSIM3). Just to point out, the calculations that you do using a long-channel MOS model are implicitly source-oriented as well and should suffer from some errors that the simulator will also make.

I could try to explain a bit about why the body effect does not come into play with series transistors when looking at MOS operation in a bulk-oriented viewpoint, but I think there are others who can do a much better job.

Tsividis and the EKV model people both provide very good literature on how the MOS transistor should be modelled. Perhaps a look at their books/papers would be useful for you, but as Rob points out, don't hope to be able to simulate series transistors accurately anytime soon. Acually, simulation models always will have errors, and although BSIM3 has quite many, it is unlikely to be replaced soon as all companies and foundries have invested too heavily into these.

For now, the best answer to your original question may be found by delving into:

Yannis Tsividis - Operation & Modelling of the MOS Transistor
EKV model literature can be found online by searching their homepage.

Regards
Vivek

Title: Re: Series transistors
Post by Croaker on Dec 1^st, 2006, 4:44am

Vivkr,

You can prove that two series transistors are equal to one double-length transistor by setting the current eqn for each FET to be equal.

The bottom one is always in triode, and the top one can be triode or sat. Then you just re-arrange until you make one side of the eqn look like the current for a double-length transistor.

E.g.

I1( in triode ) = I2 ( saturation )
or
I1 ( in triode ) = I2 ( triode )

To get an answer such that Lseries = 2 * L, you need to assume that Vth1 = Vth2. If Vth2 != Vth1, you get an extra term.

As for the bulk-effect not mattering, for a series chain, it should physically not be different from a long transistor (as you said). I guess you could say any point in the channel of the long transistor could be considered a source, and this source will have body-effect because it is not at the same potential as the reference source (actual source of long device).

As for the proof discussed above, I think body-effect does matter, but as RobG mentioned, something else (not considered) cancels it out.

Marc

Title: Re: Series transistors
Post by Croaker on Dec 1^st, 2006, 5:01am

OK, I remember reading about symmetrical models. It was the ACM model and there are some good papers on it as well as a detailed write-up in the Low-voltage book by Sanchez-Sinencio. I believe EKV is symmetrical as well. I heard PSP is also a good new model to use.

It strikes me as a pretty odd situation if the most widely used BSIM model can't even handle series MOSFETs properly! :o

Title: Re: Series transistors
Post by vivkr on Dec 1^st, 2006, 7:28am

Croaker wrote on Dec 1^st, 2006, 4:44am:

Vivkr,

As for the proof discussed above, I think body-effect does matter, but as RobG mentioned, something else (not considered) cancels it out.

Marc

Hi Marc,

Let me recast your statement a little differently. The "body effect" does not matter. As you very rightly deduced from my previous posts, one can split a single MOS into as many sub-devices as one wishes, each with its own source and drain and each haveing its source at a different potential and hence seeing different amounts of body effect so to speak, from a source-oriented model perspective.

You have tempted me to try to explain something which I am not sure I understand well enough. So please excuse the various errors that I am source to make, but here goes:

Looking at the above MOS structure from a charge perspective, you have the gate, bulk and the source and drain which are for all purposes
identical.

First, there is no voltage at either source/drain and you raise gate with respect to bulk (we are talking NMOS), you will induce a charge throughout
the channel. At any point, the charge in the channel is proportional to V(G) - V(x), where x is the position in channel between source and drain.

So, Q(x) ~ Cox( V(G) - V(x) -Vt0 )

Applying a finite +ve potential at Drain or Source will change V(x) at various points in the channel, reducing the Q(x) at various points in
response to increase in V(S) and/or V(D).

When V(S) goes up wrt V(B), the channel pinches off at Source, when V(D) goes up wrt V(B), the channel pinches off at drain. This identical phenomenon (in my opinion) are recast as "channel turn-off" and "drain pinchoff" when talking in source-oriented terms.

The fact that the channel charge at every single point is determined by V(G), V(x) wrt V(B) automatically should tell you that it is not a question of the "body effect" being absorbed anywhere, it is always there at each point in the channel. If it causes some of the transistors in your series arrangement to be "cut-off", then this does not mean that you have turned off the structure, only that the top ones behave like the pinched off end of a single MOS.

Since the channel potential is a strictly monotonic function of V(D) and V(S), we are used to oversimplification, and always think of the "body effect" as belonging to the source and to the source end alone.

Perhaps that is the problem. As to your other comment, yes it is unfortunate that such a simple and widely used structure cannot be simulate correctly. I would strongly advise you to look at the book by Tsividis. There is an excellent chapter on benchmarking models where he explains how to find out if your models are wirth using or not. I believe it is last chapter on modelling.

Regards
Vivek

Title: Re: Series transistors
Post by Croaker on Dec 1^st, 2006, 7:48am

Yup, I agree. What you just said was what I meant when I said this:

"I guess you could say any point in the channel of the long transistor could be considered a source, and this source will have body-effect because it is not at the same potential as the reference source (actual source of long device)."

In case that isn't clear, what I meant was that you can break a long transistor anywhere in the channel and say it's one transistor with body-effect and one without. So, there is body-effect for the FET with its source not at the bulk potential, but as you pointed out several posts ago, this doesn't change the end result...it's still just a long transistor.

When I said the body-effect still matters, I was thinking about the simple derivation I did with the error term. I meant that there is probably a way to do a more detailed derivation where another factor eliminates the body-effect error term.

So, I think we can stop this line of discussion.

The conclusion I'm drawing from RobG's posts are that BSIM models can't be trusted to give the right results for series transistors. And, the right result is that there should be no difference between series transistors and a long transistor.

But really, I think the change in Vth with L really negates the whole idea that the series chain is the exact same as a long transistor!!!