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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Generate a task https://designers-guide.org/forum/YaBB.pl?num=1162994138 Message started by Pinhead on Nov 8th, 2006, 5:55am |
Title: Generate a task Post by Pinhead on Nov 8th, 2006, 5:55am Hi Everybody!! I'm trying to create some parallel tasks using the generate statement. task mytask; input din; endtask genvar i; generate for (i=0;i<5;i=i+1) begin: Gen mytask(ain); end endgenerate When i try to do this, the compiler gives me the error message that it can't find "mytask" in the design library, like it's looking for a module named mytask. I'm using AMS Designer. HELP! |
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